Archives are refreshed every 15 minutes - for details, please visit
the main index
.
You can also
download the archives in mbox format
.
qemu-riscv (date)
[
Thread Index
][
Top
][
All Lists
][
qemu-riscv info page
]
Advanced
[
Prev Period
]
Last Modified: Fri Jan 31 2020 20:11:07 -0500
Messages in reverse chronological order
[
Next Period
]
January 31, 2020
[PATCH v2 35/35] target/riscv: Allow enabling the Hypervisor extension
,
Alistair Francis
,
20:11
[PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro
,
Alistair Francis
,
20:11
[PATCH v2 33/35] target/riscv: Add support for the 32-bit MSTATUSH CSR
,
Alistair Francis
,
20:11
[PATCH v2 31/35] target/riscv: Raise the new execptions when 2nd stage translation fails
,
Alistair Francis
,
20:10
[PATCH v2 30/35] target/riscv: Implement second stage MMU
,
Alistair Francis
,
20:10
[PATCH v2 29/35] target/riscv: Allow specifying MMU stage
,
Alistair Francis
,
20:10
[PATCH v2 32/35] target/riscv: Set htval and mtval2 on execptions
,
Alistair Francis
,
20:10
[PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty
,
Alistair Francis
,
20:10
[PATCH v2 28/35] target/riscv: Respect MPRV and SPRV for floating point ops
,
Alistair Francis
,
20:10
[PATCH v2 26/35] target/riscv: Disable guest FP support based on virtual status
,
Alistair Francis
,
20:10
[PATCH v2 23/35] target/riscv: Add hfence instructions
,
Alistair Francis
,
20:10
[PATCH v2 24/35] target/riscv: Remove the hret instruction
,
Alistair Francis
,
20:10
[PATCH v2 22/35] target/riscv: Add Hypervisor trap return support
,
Alistair Francis
,
20:10
[PATCH v2 25/35] target/riscv: Only set TB flags with FP status if enabled
,
Alistair Francis
,
20:09
[PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when V=1
,
Alistair Francis
,
20:09
[PATCH v2 19/35] target/ricsv: Flush the TLB on virtulisation mode changes
,
Alistair Francis
,
20:09
[PATCH v2 21/35] target/riscv: Add hypvervisor trap support
,
Alistair Francis
,
20:09
[PATCH v2 18/35] target/riscv: Add support for virtual interrupt setting
,
Alistair Francis
,
20:09
[PATCH v2 16/35] target/riscv: Extend the MIE CSR to support virtulisation
,
Alistair Francis
,
20:09
[PATCH v2 15/35] target/riscv: Set VS bits in mideleg for Hyp extension
,
Alistair Francis
,
20:09
[PATCH v2 17/35] target/riscv: Extend the SIP CSR to support virtulisation
,
Alistair Francis
,
20:09
[PATCH v2 14/35] target/riscv: Add virtual register swapping function
,
Alistair Francis
,
20:09
[PATCH v2 13/35] target/riscv: Add Hypervisor machine CSRs accesses
,
Alistair Francis
,
20:08
[PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses
,
Alistair Francis
,
20:08
[PATCH v2 11/35] target/riscv: Add Hypervisor CSR access functions
,
Alistair Francis
,
20:08
[PATCH v2 10/35] target/riscv: Dump Hypervisor registers if enabled
,
Alistair Francis
,
20:08
[PATCH v2 09/35] target/riscv: Print priv and virt in disas log
,
Alistair Francis
,
20:08
[PATCH v2 08/35] target/riscv: Fix CSR perm checking for HS mode
,
Alistair Francis
,
20:08
[PATCH v2 07/35] target/riscv: Add the force HS exception mode
,
Alistair Francis
,
20:08
[PATCH v2 06/35] target/riscv: Add the virtulisation mode
,
Alistair Francis
,
20:08
[PATCH v2 05/35] target/riscv: Rename the H irqs to VS irqs
,
Alistair Francis
,
20:08
[PATCH v2 04/35] target/riscv: Add support for the new execption numbers
,
Alistair Francis
,
20:08
[PATCH v2 03/35] target/riscv: Add the Hypervisor CSRs to CPUState
,
Alistair Francis
,
20:08
[PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5
,
Alistair Francis
,
20:08
[PATCH v2 02/35] target/riscv: Add the Hypervisor extension
,
Alistair Francis
,
20:08
[PATCH v2 01/35] target/riscv: Convert MIP CSR to target_ulong
,
Alistair Francis
,
20:08
Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers
,
Alistair Francis
,
19:16
Re: [PATCH v1 23/36] target/riscv: Add hypvervisor trap support
,
Alistair Francis
,
16:32
Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers
,
Alistair Francis
,
12:38
Re: [PATCH rc2 12/25] hw/timer: Add limited support for Atmel 16 bit timer peripheral
,
Philippe Mathieu-Daudé
,
06:21
January 30, 2020
Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Philippe Mathieu-Daudé
,
20:36
Re: [PATCH rc2 12/25] hw/timer: Add limited support for Atmel 16 bit timer peripheral
,
Aleksandar Markovic
,
17:45
Re: [PATCH rc2 12/25] hw/timer: Add limited support for Atmel 16 bit timer peripheral
,
Aleksandar Markovic
,
17:44
Re: [PATCH] riscv: Separate FPU register size from core register size in gdbstub [v2]
,
Keith Packard
,
17:13
Re: [PATCH] riscv: Separate FPU register size from core register size in gdbstub [v2]
,
Palmer Dabbelt
,
15:49
Re: [PATCH v2] riscv/virt: Add syscon reboot and poweroff DT nodes
,
Palmer Dabbelt
,
10:41
Re: [PATCH v2 2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation
,
Anup Patel
,
10:28
Re: [PATCH v2 1/2] target/riscv: Emulate TIME CSRs for privileged mode
,
Anup Patel
,
10:22
Re: [PATCH v2 2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation
,
Palmer Dabbelt
,
09:49
Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers
,
Palmer Dabbelt
,
09:48
Re: [PATCH v2 1/2] target/riscv: Emulate TIME CSRs for privileged mode
,
Palmer Dabbelt
,
09:44
Re: [PATCH] riscv: Add semihosting support [v4]
,
Peter Maydell
,
07:02
Re: [PATCH] riscv: Add semihosting support [v4]
,
Palmer Dabbelt
,
06:38
Re: [PATCH] riscv: Add semihosting support [v4]
,
Peter Maydell
,
05:54
January 29, 2020
Re: [PATCH] riscv: Add semihosting support [v4]
,
Jonathan Behrens
,
13:07
Re: [PATCH] riscv: Add semihosting support [v4]
,
Keith Packard
,
11:45
Re: [PATCH] riscv: Add semihosting support [v4]
,
Peter Maydell
,
10:58
Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
,
Palmer Dabbelt
,
10:29
January 28, 2020
Re: [PATCH] riscv: Add semihosting support [v3]
,
Keith Packard
,
18:47
[PATCH] riscv: Add semihosting support [v4]
,
Keith Packard
,
18:47
[PATCH] riscv: Separate FPU register size from core register size in gdbstub
,
Keith Packard
,
18:47
Re: [PATCH] riscv: Separate FPU register size from core register size in gdbstub
,
Keith Packard
,
18:47
[PATCH] riscv: Separate FPU register size from core register size in gdbstub [v2]
,
Keith Packard
,
18:47
[PATCH] riscv: Add semihosting support [v3]
,
Keith Packard
,
18:47
Re: [PATCH] riscv: Add semihosting support [v3]
,
no-reply
,
18:47
Re: [PATCH] riscv: Separate FPU register size from core register size in gdbstub
,
no-reply
,
18:37
Re: [PATCH] riscv: Separate FPU register size from core register size in gdbstub [v2]
,
Alistair Francis
,
18:35
Re: [PATCH] riscv: Separate FPU register size from core register size in gdbstub
,
Alistair Francis
,
18:27
Re: [PATCH] riscv: Separate FPU register size from core register size in gdbstub
,
no-reply
,
17:47
[PATCH] riscv/target: fix vs interrupt delegation
,
Jose Martins
,
12:12
January 27, 2020
Re: [PATCH v2] riscv/virt: Add syscon reboot and poweroff DT nodes
,
Alistair Francis
,
18:25
Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1
,
Palmer Dabbelt
,
14:23
Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Michael Rolnik
,
08:39
Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Joaquin de Andres
,
08:27
Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Joaquin de Andres
,
05:40
Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Michael Rolnik
,
04:49
Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Joaquin de Andres
,
04:24
Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Michael Rolnik
,
03:54
Re: [PATCH rc2 20/25] hw/avr: Add some ATmega microcontrollers
,
Aleksandar Markovic
,
03:05
Re: [PATCH rc2 20/25] hw/avr: Add some ATmega microcontrollers
,
Philippe Mathieu-Daudé
,
02:59
January 26, 2020
Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Aleksandar Markovic
,
21:25
Re: [PATCH rc2 20/25] hw/avr: Add some ATmega microcontrollers
,
Aleksandar Markovic
,
09:46
Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Joaquin de Andres
,
07:15
January 25, 2020
Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Thomas Huth
,
12:08
Re: [PATCH rc2 21/25] hw/avr: Add some Arduino boards
,
Joaquin de Andres
,
08:27
Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Aleksandar Markovic
,
05:49
January 24, 2020
Re: [PATCH rc2 00/25] target/avr merger
,
Michael Rolnik
,
09:51
Re: [PATCH rc2 12/25] hw/timer: Add limited support for Atmel 16 bit timer peripheral
,
Sarah Harris
,
09:51
Re: [PATCH rc2 14/25] target/avr: Add section about AVR into QEMU documentation
,
Michael Rolnik
,
09:51
Re: [PATCH rc2 00/25] target/avr merger
,
Michael Rolnik
,
09:51
Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1
,
Peter Maydell
,
08:23
Re: [PATCH rc2 12/25] hw/timer: Add limited support for Atmel 16 bit timer peripheral
,
Philippe Mathieu-Daudé
,
07:53
Re: [PATCH rc2 12/25] hw/timer: Add limited support for Atmel 16 bit timer peripheral
,
Philippe Mathieu-Daudé
,
07:50
Re: [PATCH rc2 00/25] target/avr merger
,
Philippe Mathieu-Daudé
,
07:49
Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1
,
Peter Maydell
,
07:35
Re: [PATCH rc2 22/25] target/avr: Update build system
,
Alex Bennée
,
05:59
Re: [PATCH rc2 12/25] hw/timer: Add limited support for Atmel 16 bit timer peripheral
,
Philippe Mathieu-Daudé
,
05:52
Re: [PATCH rc2 12/25] hw/timer: Add limited support for Atmel 16 bit timer peripheral
,
Alex Bennée
,
05:42
Re: [PATCH rc2 12/25] hw/timer: Add limited support for Atmel 16 bit timer peripheral
,
Thomas Huth
,
03:16
Re: [PATCH rc2 14/25] target/avr: Add section about AVR into QEMU documentation
,
Thomas Huth
,
02:14
Re: [PATCH rc2 00/25] target/avr merger
,
Thomas Huth
,
02:12
January 23, 2020
Re: [PATCH] target/riscv: Disallow WFI instruction from U-mode
,
Jonathan Behrens
,
22:23
Re: [PATCH rc2 00/25] target/avr merger
,
Philippe Mathieu-Daudé
,
20:03
[PATCH rc2 25/25] .travis.yml: Run the AVR acceptance tests
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 24/25] tests/acceptance: Test the Arduino MEGA2560 board
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 20/25] hw/avr: Add some ATmega microcontrollers
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 23/25] tests/boot-serial-test: Test some Arduino boards (AVR based)
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 22/25] target/avr: Update build system
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 21/25] hw/avr: Add some Arduino boards
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 19/25] hw/avr: Add helper to load raw/ELF firmware binaries
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 18/25] hw/core/loader: Let load_elf populate the processor-specific flags
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 17/25] target/avr: Update MAINTAINERS file
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 16/25] target/avr: Add machine none test
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 12/25] hw/timer: Add limited support for Atmel 16 bit timer peripheral
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 15/25] target/avr: Register AVR support with the rest of QEMU
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 14/25] target/avr: Add section about AVR into QEMU documentation
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 13/25] hw/misc: Add Atmel power device
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 11/25] hw/char: Add limited support for Atmel USART peripheral
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 06/25] target/avr: Add instruction translation - Data Transfer Instructions
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 10/25] target/avr: Add instruction disassembly function
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 09/25] target/avr: Add instruction translation - CPU main translation function
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 08/25] target/avr: Add instruction translation - MCU Control Instructions
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 04/25] target/avr: Add instruction translation - Arithmetic and Logic Instructions
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 07/25] target/avr: Add instruction translation - Bit and Bit-test Instructions
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 05/25] target/avr: Add instruction translation - Branch Instructions
,
Philippe Mathieu-Daudé
,
19:52
[PATCH rc2 02/25] target/avr: Add instruction helpers
,
Philippe Mathieu-Daudé
,
19:51
[PATCH rc2 03/25] target/avr: Add instruction translation - Registers definition
,
Philippe Mathieu-Daudé
,
19:51
[PATCH rc2 00/25] target/avr merger
,
Philippe Mathieu-Daudé
,
19:51
Re: [PATCH] target/riscv: Disallow WFI instruction from U-mode
,
Richard Henderson
,
18:35
[PATCH] target/riscv: Disallow WFI instruction from U-mode
,
Jonathan Behrens
,
14:53
Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1
,
Palmer Dabbelt
,
13:43
Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1
,
Peter Maydell
,
09:38
January 22, 2020
Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers
,
Jonathan Behrens
,
17:15
[PATCH v2] riscv/virt: Add syscon reboot and poweroff DT nodes
,
Anup Patel
,
08:17
Re: [PATCH v8 0/3] RTC support for QEMU RISC-V virt machine
,
Anup Patel
,
06:43
[PATCH v2 2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation
,
Anup Patel
,
06:30
[PATCH v2 1/2] target/riscv: Emulate TIME CSRs for privileged mode
,
Anup Patel
,
06:30
[PATCH v2 0/2] RISC-V TIME CSR for privileged mode
,
Anup Patel
,
06:30
January 21, 2020
Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers
,
Alistair Francis
,
19:01
[PULL 5/5] target/riscv: update mstatus.SD when FS is set dirty
,
Palmer Dabbelt
,
18:41
[PULL 4/5] target/riscv: fsd/fsw doesn't dirty FP state
,
Palmer Dabbelt
,
18:41
[PULL 2/5] riscv: Set xPIE to 1 after xRET
,
Palmer Dabbelt
,
18:41
[PULL 3/5] target/riscv: Fix tb->flags FS status
,
Palmer Dabbelt
,
18:41
[PULL 1/5] riscv/sifive_u: fix a memory leak in soc_realize()
,
Palmer Dabbelt
,
18:41
[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1
,
Palmer Dabbelt
,
18:41
Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
,
Alistair Francis
,
17:26
Re: [Qemu-devel] [PATCH] target/riscv: Disallow WFI instruction from U-mode
,
Alistair Francis
,
17:25
Re: [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled
,
Alistair Francis
,
17:21
Re: [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled
,
Aurelien Jarno
,
15:37
Re: [Qemu-devel] [PATCH] target/riscv: Disallow WFI instruction from U-mode
,
Jonathan Behrens
,
08:21
Re: [PATCH v1 1/1] target/riscv: Correctly implement TSR trap
,
Jonathan Behrens
,
08:19
Re: [PATCH 0/2] RISC-V TIME CSR for privileged mode
,
Jonathan Behrens
,
08:11
Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
,
Jonathan Behrens
,
08:06
Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers
,
Jonathan Behrens
,
07:56
Re: [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension
,
Anup Patel
,
06:29
Re: [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension
,
Alistair Francis
,
06:12
Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers
,
Alistair Francis
,
06:02
Re: [PATCH 2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation
,
Alistair Francis
,
05:44
Re: [PATCH 1/2] target/riscv: Emulate TIME CSRs for privileged mode
,
Alistair Francis
,
05:44
[PATCH 2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation
,
Anup Patel
,
04:00
[PATCH 1/2] target/riscv: Emulate TIME CSRs for privileged mode
,
Anup Patel
,
03:59
[PATCH 0/2] RISC-V TIME CSR for privileged mode
,
Anup Patel
,
03:59
[PATCH v1 1/1] target/riscv: Correctly implement TSR trap
,
Alistair Francis
,
00:43
January 20, 2020
RE: [PATCH v1 23/36] target/riscv: Add hypvervisor trap support
,
Jiangyifei
,
03:35
January 19, 2020
Re: [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled
,
Alistair Francis
,
19:32
January 17, 2020
Re: [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
,
Alistair Francis
,
07:09
January 16, 2020
Re: [PATCH v5 08/22] gdbstub: extend GByteArray to read register helpers
,
Damien Hedde
,
04:59
January 15, 2020
Re: [PATCH v3 1/3] target/riscv: Fix tb->flags FS status
,
Alistair Francis
,
18:07
Re: [PATCH v3 1/3] target/riscv: Fix tb->flags FS status
,
Richard Henderson
,
16:46
Re: [PATCH v3 1/3] target/riscv: Fix tb->flags FS status
,
ShihPo Hung
,
09:27
Re: [PATCH v3 3/3] target/riscv: update mstatus.SD when FS is set dirty
,
Alistair Francis
,
01:31
Re: [PATCH v3 2/3] target/riscv: fsd/fsw doesn't dirty FP state
,
Alistair Francis
,
01:30
Re: [PATCH v3 1/3] target/riscv: Fix tb->flags FS status
,
Alistair Francis
,
01:29
[PATCH v3 3/3] target/riscv: update mstatus.SD when FS is set dirty
,
shihpo . hung
,
01:17
[PATCH v3 1/3] target/riscv: Fix tb->flags FS status
,
shihpo . hung
,
01:17
[PATCH v3 2/3] target/riscv: fsd/fsw doesn't dirty FP state
,
shihpo . hung
,
01:17
Re: [PATCH v2 1/3] target/riscv: Fix tb->flags FS status
,
ShihPo Hung
,
01:16
Re: [PATCH v5 08/22] gdbstub: extend GByteArray to read register helpers
,
David Gibson
,
00:57
January 14, 2020
Re: [PATCH v2 2/3] target/riscv: fsd/fsw doesn't dirty FP state
,
Richard Henderson
,
10:48
Re: [PATCH v2 3/3] target/riscv: update mstatus.SD when FS is set dirty
,
Richard Henderson
,
10:47
Re: [PATCH v2 1/3] target/riscv: Fix tb->flags FS status
,
Richard Henderson
,
10:29
[PATCH v5 08/22] gdbstub: extend GByteArray to read register helpers
,
Alex Bennée
,
10:10
[PATCH v2 3/3] target/riscv: update mstatus.SD when FS is set dirty
,
shihpo . hung
,
05:15
[PATCH v2 2/3] target/riscv: fsd/fsw doesn't dirty FP state
,
shihpo . hung
,
05:14
[PATCH v2 1/3] target/riscv: Fix tb->flags FS status
,
shihpo . hung
,
05:14
Re: [PATCH] target/riscv: Set mstatus.DS & FS correctly
,
ShihPo Hung
,
04:23
January 13, 2020
Re: [PATCH] target/riscv: Set mstatus.DS & FS correctly
,
Richard Henderson
,
21:32
Re: [PATCH 3/3] remove redundant check for fpu csr read and write interface
,
Richard Henderson
,
21:24
Re: [PATCH 2/3] RISC-V: use FIELD macro to define tb flags
,
Richard Henderson
,
21:22
January 10, 2020
Re: [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting
,
Palmer Dabbelt
,
18:21
[PATCH] target/riscv: Set mstatus.DS & FS correctly
,
shihpo . hung
,
08:48
[PATCH 3/3] remove redundant check for fpu csr read and write interface
,
LIU Zhiwei
,
03:13
[PATCH 2/3] RISC-V: use FIELD macro to define tb flags
,
LIU Zhiwei
,
03:13
[PATCH 1/3] select gdb fpu xml by single or double float extension
,
LIU Zhiwei
,
03:13
Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
,
Bin Meng
,
02:52
January 09, 2020
Re: [PATCH] riscv/sifive_u: fix a memory leak in soc_realize()
,
Palmer Dabbelt
,
18:42
January 08, 2020
Re: [PATCH v1 35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro
,
Palmer Dabbelt
,
21:36
Re: [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting
,
Richard Henderson
,
21:33
Re: [PATCH v1 34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR
,
Palmer Dabbelt
,
21:29
Re: [PATCH v1 33/36] target/riscv: Set htval and mtval2 on execptions
,
Palmer Dabbelt
,
21:29
Re: [PATCH v1 32/36] target/riscv: Raise the new execptions when 2nd stage translation fails
,
Palmer Dabbelt
,
21:29
Re: [PATCH v1 31/36] target/riscv: Implement second stage MMU
,
Palmer Dabbelt
,
21:01
Re: [PATCH v1 30/36] target/riscv: Allow specifying MMU stage
,
Palmer Dabbelt
,
20:41
Re: [PATCH v1 29/36] target/riscv: Respect MPRV and SPRV for floating point ops
,
Palmer Dabbelt
,
19:59
Re: [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting
,
Palmer Dabbelt
,
19:49
Re: [PATCH v1 19/36] target/riscv: Extend the SIP CSR to support virtulisation
,
Palmer Dabbelt
,
19:49
Re: [PATCH v1 26/36] target/riscv: Remove the hret instruction
,
Palmer Dabbelt
,
19:49
Re: [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation
,
Palmer Dabbelt
,
15:25
January 07, 2020
Re: [Qemu-devel] [PATCH v2 05/17] RISC-V: add vector extension load and store instructions
,
Richard Henderson
,
21:08
Re: [PATCH v1 16/36] target/riscv: Add virtual register swapping function
,
Palmer Dabbelt
,
21:07
Re: [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension
,
Palmer Dabbelt
,
21:07
Re: [Qemu-devel] [PATCH v2 05/17] RISC-V: add vector extension load and store instructions
,
LIU Zhiwei
,
20:32
Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers
,
Palmer Dabbelt
,
20:31
Re: [PATCH v1 14/36] target/riscv: Add Hypervisor virtual CSRs accesses
,
Palmer Dabbelt
,
19:08
Re: [PATCH v1 12/36] target/riscv: Add Hypervisor CSR access functions
,
Palmer Dabbelt
,
19:08
Re: [PATCH v1 09/36] target/riscv: Fix CSR perm checking for HS mode
,
Palmer Dabbelt
,
19:06
Re: [PATCH v1 06/36] target/riscv: Rename the H irqs to VS irqs
,
Palmer Dabbelt
,
13:28
Re: [PATCH v1 05/36] target/riscv: Add support for the new execption numbers
,
Palmer Dabbelt
,
13:28
Re: [PATCH v1 07/36] target/riscv: Add the virtulisation mode
,
Palmer Dabbelt
,
13:28
Re: [PATCH v1 04/36] target/riscv: Add the Hypervisor CSRs to CPUState
,
Palmer Dabbelt
,
13:28
Re: [PATCH v2 00/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef
,
Paolo Bonzini
,
10:23
Re: [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
,
Alex Bennée
,
06:26
Re: [PATCH v2 0/4] tcg: Include tcg files using tcg/ dirname, reduce cpp search path list
,
Paolo Bonzini
,
05:55
Re: [PATCH v2 2/4] tcg: Search includes in the parent source directory
,
Paolo Bonzini
,
05:54
January 06, 2020
Re: [PATCH v3 4/4] RISC-V: add vector extension configure instruction
,
LIU Zhiwei
,
21:11
Re: [PATCH v3 2/4] RISC-V: configure and turn on vector extension from command line
,
LIU Zhiwei
,
20:42
Re: [PATCH v3 3/4] RISC-V: support vector extension csr
,
LIU Zhiwei
,
20:34
Re: [PATCH v1 02/36] target/riscv: Don't set write permissions on dirty PTEs
,
Alistair Francis
,
20:34
Re: [PATCH v3 3/4] RISC-V: support vector extension csr
,
Jim Wilson
,
17:01
Re: [PATCH v3 2/4] RISC-V: configure and turn on vector extension from command line
,
Jim Wilson
,
16:48
Re: [PATCH v1 02/36] target/riscv: Don't set write permissions on dirty PTEs
,
Palmer Dabbelt
,
12:51
January 05, 2020
Re: [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled
,
Aurelien Jarno
,
12:11
Re: [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled
,
Aurelien Jarno
,
12:11
January 03, 2020
Re: [PATCH v3 4/4] RISC-V: add vector extension configure instruction
,
Richard Henderson
,
18:41
Re: [PATCH v3 3/4] RISC-V: support vector extension csr
,
Richard Henderson
,
18:14
Re: [PATCH v3 2/4] RISC-V: configure and turn on vector extension from command line
,
Richard Henderson
,
18:08
Re: [PATCH v3 1/4] RISC-V: add vector extension field in CPURISCVState
,
Richard Henderson
,
18:05
Re: [PATCH] riscv: Set xPIE to 1 after xRET
,
Alistair Francis
,
14:25
Re: [PATCH] riscv: Set xPIE to 1 after xRET
,
Bin Meng
,
09:23
[PATCH] riscv: Set xPIE to 1 after xRET
,
Yiting Wang
,
03:01
January 02, 2020
[PATCH v3 4/4] RISC-V: add vector extension configure instruction
,
LIU Zhiwei
,
22:39
[PATCH v3 3/4] RISC-V: support vector extension csr
,
LIU Zhiwei
,
22:39
[PATCH v3 0/4] RISC-V: support vector extension part 1
,
LIU Zhiwei
,
22:39
[PATCH v3 2/4] RISC-V: configure and turn on vector extension from command line
,
LIU Zhiwei
,
22:39
[PATCH v3 1/4] RISC-V: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
22:39
Re: [PATCH v2 4/4] configure: Remove tcg/ from the preprocessor include search list
,
Alistair Francis
,
21:43
Re: [PATCH v2 3/4] tcg: Move TCG headers to include/tcg/
,
Alistair Francis
,
21:42
Re: [PATCH v2 2/4] tcg: Search includes in the parent source directory
,
Alistair Francis
,
21:42
Re: [PATCH v2 1/4] tcg: Search includes from the project root source directory
,
Alistair Francis
,
21:41
Re: [PATCH v1 01/36] target/riscv: Convert MIP CSR to target_ulong
,
Alistair Francis
,
21:09
Re: [PATCH v2 0/4] tcg: Include tcg files using tcg/ dirname, reduce cpp search path list
,
Richard Henderson
,
20:20
Re: [PATCH v1 01/36] target/riscv: Convert MIP CSR to target_ulong
,
Palmer Dabbelt
,
13:19
Re: [PATCH v2 0/4] tcg: Include tcg files using tcg/ dirname, reduce cpp search path list
,
Stefan Weil
,
03:46
January 01, 2020
Re: [PATCH v2 1/4] tcg: Search includes from the project root source directory
,
David Gibson
,
21:02
Re: [PATCH v2 2/4] tcg: Search includes in the parent source directory
,
David Gibson
,
21:02
[PATCH v2 4/4] configure: Remove tcg/ from the preprocessor include search list
,
Philippe Mathieu-Daudé
,
06:24
[PATCH v2 3/4] tcg: Move TCG headers to include/tcg/
,
Philippe Mathieu-Daudé
,
06:24
[PATCH v2 2/4] tcg: Search includes in the parent source directory
,
Philippe Mathieu-Daudé
,
06:23
[PATCH v2 1/4] tcg: Search includes from the project root source directory
,
Philippe Mathieu-Daudé
,
06:23
[PATCH v2 0/4] tcg: Include tcg files using tcg/ dirname, reduce cpp search path list
,
Philippe Mathieu-Daudé
,
06:23
[
Prev Period
]
[
Next Period
]
Mail converted by
MHonArc