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[PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC
From: |
Palmer Dabbelt |
Subject: |
[PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC |
Date: |
Tue, 21 Apr 2020 12:10:00 -0700 |
From: Alistair Francis <address@hidden>
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to the sifive_u SoC to specify
the board serial number. When not given, the default serial number
1 is used.
Suggested-by: Bin Meng <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 8 +++++++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index d0ea6803db..9bfd16d2bb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -492,7 +492,6 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_SIFIVE_U_PRCI);
sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
TYPE_SIFIVE_U_OTP);
- qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
TYPE_CADENCE_GEM);
}
@@ -585,6 +584,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
@@ -611,10 +611,16 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
}
+static Property riscv_sifive_u_soc_props[] = {
+ DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ device_class_set_props(dc, riscv_sifive_u_soc_props);
dc->realize = riscv_sifive_u_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 82667b5746..a2baa1de5f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -42,6 +42,8 @@ typedef struct SiFiveUSoCState {
SiFiveUPRCIState prci;
SiFiveUOTPState otp;
CadenceGEMState gem;
+
+ uint32_t serial;
} SiFiveUSoCState;
#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
--
2.26.1.301.g55bc3eb7cb9-goog
- [PULL] RISC-V Patches for 5.0-rc4, Palmer Dabbelt, 2020/04/21
- [PULL 2/6] riscv: Don't use stage-2 PTE lookup protection flags, Palmer Dabbelt, 2020/04/21
- [PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs, Palmer Dabbelt, 2020/04/21
- [PULL 3/6] riscv: AND stage-1 and stage-2 protection flags, Palmer Dabbelt, 2020/04/21
- [PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC,
Palmer Dabbelt <=
- [PULL 6/6] riscv/sifive_u: Add a serial property to the sifive_u machine, Palmer Dabbelt, 2020/04/21
- [PULL 4/6] riscv/sifive_u: Fix up file ordering, Palmer Dabbelt, 2020/04/21
- Re: [PULL] RISC-V Patches for 5.0-rc4, Peter Maydell, 2020/04/21