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qemu-riscv (date)
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Last Modified: Thu Apr 30 2020 17:48:17 -0400
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April 30, 2020
Re: [PATCH 1/1] target/riscv: fix VS interrupts forwarding to HS
,
Jose Martins
,
17:48
Re: [PATCH] target/riscv: fix check of guest pa top bits
,
Alistair Francis
,
17:36
Re: [PATCH] target/riscv: fix check of guest pa top bits
,
Alistair Francis
,
15:56
Re: [PATCH 1/1] target/riscv: fix VS interrupts forwarding to HS
,
Alistair Francis
,
15:44
Re: [PULL v2 00/14] RISC-V Patch Queue for 5.1
,
Peter Maydell
,
07:52
[RFC PATCH 2/8] riscv: Generate payload scripts
,
LIU Zhiwei
,
03:24
[RFC PATCH 4/8] riscv: Implement payload load interfaces
,
LIU Zhiwei
,
03:24
[RFC PATCH 8/8] riscv: Add RV64F instructions description
,
LIU Zhiwei
,
03:24
[RFC PATCH 1/8] riscv: Add RV64I instructions description
,
LIU Zhiwei
,
03:24
[RFC PATCH 7/8] riscv: Add RV64M instructions description
,
LIU Zhiwei
,
03:24
[RFC PATCH 3/8] riscv: Define riscv struct reginfo
,
LIU Zhiwei
,
03:24
[RFC PATCH 6/8] riscv: Add configure script
,
LIU Zhiwei
,
03:24
[RFC PATCH 0/8] RISCV risu porting
,
LIU Zhiwei
,
03:24
[RFC PATCH 5/8] riscv: Add standard test case
,
LIU Zhiwei
,
03:24
April 29, 2020
Re: [PATCH 1/1] target/riscv: fix VS interrupts forwarding to HS
,
Jose Martins
,
17:08
[PULL v2 11/14] roms: opensbi: Upgrade from v0.6 to v0.7
,
Alistair Francis
,
16:33
Re: [PULL 00/14] RISC-V Patch Queue for 5.1
,
Alistair Francis
,
16:33
[PULL v2 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option
,
Alistair Francis
,
16:33
[PULL v2 14/14] hw/riscv/spike: Allow more than one CPUs
,
Alistair Francis
,
16:33
[PULL v2 10/14] linux-user/riscv: fix up struct target_ucontext definition
,
Alistair Francis
,
16:33
[PULL v2 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
,
Alistair Francis
,
16:33
[PULL v2 08/14] riscv: sifive_e: Support changing CPU type
,
Alistair Francis
,
16:33
[PULL v2 09/14] target/riscv: Add a sifive-e34 cpu type
,
Alistair Francis
,
16:33
[PULL v2 05/14] riscv: AND stage-1 and stage-2 protection flags
,
Alistair Francis
,
16:33
[PULL v2 06/14] riscv: Fix Stage2 SV32 page table walk
,
Alistair Francis
,
16:33
[PULL v2 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines
,
Alistair Francis
,
16:32
[PULL v2 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine
,
Alistair Francis
,
16:32
[PULL v2 04/14] riscv: Don't use stage-2 PTE lookup protection flags
,
Alistair Francis
,
16:32
[PULL v2 02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Alistair Francis
,
16:32
[PULL v2 00/14] RISC-V Patch Queue for 5.1
,
Alistair Francis
,
16:32
[PULL v2 01/14] riscv/sifive_u: Fix up file ordering
,
Alistair Francis
,
16:32
Re: [PULL 00/14] RISC-V Patch Queue for 5.1
,
Peter Maydell
,
16:04
Re: [PATCH 1/1] target/riscv: fix VS interrupts forwarding to HS
,
Alistair Francis
,
14:52
[PULL 11/14] roms: opensbi: Upgrade from v0.6 to v0.7
,
Alistair Francis
,
14:38
[PULL 14/14] hw/riscv/spike: Allow more than one CPUs
,
Alistair Francis
,
14:38
[PULL 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option
,
Alistair Francis
,
14:37
[PULL 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
,
Alistair Francis
,
14:37
[PULL 09/14] target/riscv: Add a sifive-e34 cpu type
,
Alistair Francis
,
14:37
[PULL 08/14] riscv: sifive_e: Support changing CPU type
,
Alistair Francis
,
14:37
[PULL 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines
,
Alistair Francis
,
14:37
[PULL 10/14] linux-user/riscv: fix up struct target_ucontext definition
,
Alistair Francis
,
14:37
[PULL 04/14] riscv: Don't use stage-2 PTE lookup protection flags
,
Alistair Francis
,
14:37
[PULL 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine
,
Alistair Francis
,
14:37
[PULL 05/14] riscv: AND stage-1 and stage-2 protection flags
,
Alistair Francis
,
14:37
[PULL 06/14] riscv: Fix Stage2 SV32 page table walk
,
Alistair Francis
,
14:37
[PULL 02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Alistair Francis
,
14:37
[PULL 01/14] riscv/sifive_u: Fix up file ordering
,
Alistair Francis
,
14:37
[PULL 00/14] RISC-V Patch Queue for 5.1
,
Alistair Francis
,
14:37
Re: [PATCH 1/1] target/riscv: fix VS interrupts forwarding to HS
,
Jose Martins
,
12:07
Re: [PATCH-for-5.1 v3 01/24] various: Remove suspicious '\' character outside of #define in C code
,
Markus Armbruster
,
02:04
April 27, 2020
Re: [PATCH 1/1] target/riscv: fix VS interrupts forwarding to HS
,
Alistair Francis
,
17:49
Re: [PATCH v3 0/3] RISC-V Spike machine improvements
,
Alistair Francis
,
11:14
Re: [PATCH v3 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
,
Alistair Francis
,
11:13
Re: [PATCH v3 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option
,
Alistair Francis
,
11:12
Re: [PATCH v3 3/3] hw/riscv/spike: Allow more than one CPUs
,
Alistair Francis
,
11:08
[PATCH v3 3/3] hw/riscv/spike: Allow more than one CPUs
,
Anup Patel
,
04:07
[PATCH v3 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
,
Anup Patel
,
04:07
[PATCH v3 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option
,
Anup Patel
,
04:07
[PATCH v3 0/3] RISC-V Spike machine improvements
,
Anup Patel
,
04:07
April 26, 2020
[PATCH v1 7/9] riscv/opentitan: Connect the PLIC device
,
Alistair Francis
,
14:03
[PATCH v1 9/9] target/riscv: Use a smaller guess size for no-MMU PMP
,
Alistair Francis
,
14:03
[PATCH v1 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC
,
Alistair Francis
,
14:03
[PATCH v1 8/9] riscv/opentitan: Connect the UART device
,
Alistair Francis
,
14:03
[PATCH v1 4/9] riscv: Initial commit of OpenTitan machine
,
Alistair Francis
,
14:03
[PATCH v1 5/9] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
14:03
[PATCH v1 3/9] target/riscv: Add the lowRISC Ibex CPU
,
Alistair Francis
,
14:03
[PATCH v1 2/9] target/riscv: Don't overwrite the reset vector
,
Alistair Francis
,
14:02
[PATCH v1 1/9] riscv/boot: Add a missing header include
,
Alistair Francis
,
14:02
[PATCH v1 0/9] RISC-V Add the OpenTitan Machine
,
Alistair Francis
,
14:02
[PATCH v1 15/15] target/riscv: Support the v0.6 Hypervisor extension CRSs
,
Alistair Francis
,
13:25
[PATCH v1 14/15] target/riscv: Only support little endian guests
,
Alistair Francis
,
12:28
[PATCH v1 11/15] target/riscv: Update the Hypervisor trap return/entry
,
Alistair Francis
,
12:28
[PATCH v1 13/15] target/riscv: Only support a single VSXL length
,
Alistair Francis
,
12:28
[PATCH v1 12/15] target/riscv: Update the CSRs to the v0.6 Hyp extension
,
Alistair Francis
,
12:28
[PATCH v1 10/15] target/riscv: Fix the interrupt cause code
,
Alistair Francis
,
12:27
[PATCH v1 09/15] target/riscv: Convert MSTATUS MTL to GVA
,
Alistair Francis
,
12:27
[PATCH v1 08/15] target/riscv: Don't allow guest to write to htinst
,
Alistair Francis
,
12:27
[PATCH v1 07/15] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
,
Alistair Francis
,
12:27
[PATCH v1 06/15] target/riscv: Allow generating hlv/hlvx/hsv instructions
,
Alistair Francis
,
12:27
[PATCH v1 04/15] target/riscv: Implement checks for hfence
,
Alistair Francis
,
12:27
[PATCH v1 05/15] target/riscv: Allow setting a two-stage lookup in the virt status
,
Alistair Francis
,
12:27
[PATCH v1 03/15] target/riscv: Move the hfence instructions to the rvh decode
,
Alistair Francis
,
12:27
[PATCH v1 01/15] target/riscv: Set access as data_load when validating stage-2 PTEs
,
Alistair Francis
,
12:27
[PATCH v1 02/15] target/riscv: Report errors validating 2nd-stage PTEs
,
Alistair Francis
,
12:27
[PATCH v1 00/15] RISC-V: Update the Hypervisor spec to v0.6
,
Alistair Francis
,
12:27
April 24, 2020
Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type
,
Alistair Francis
,
15:49
RE: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type
,
Corey Wharton
,
15:12
Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type
,
Alistair Francis
,
12:12
[PATCH] target/riscv: fix check of guest pa top bits
,
Jose Martins
,
11:09
April 23, 2020
Re: [PATCH] linux-user/riscv: fix up struct target_ucontext definition
,
Richard Henderson
,
15:45
April 22, 2020
Re: [PATCH] linux-user/riscv: fix up struct target_ucontext definition
,
LIU Zhiwei
,
21:55
Re: [PATCH] linux-user/riscv: fix up struct target_ucontext definition
,
Alistair Francis
,
17:26
Re: [PATCH] linux-user/riscv: fix up struct target_ucontext definition
,
Richard Henderson
,
15:20
Re: [PATCH] linux-user/riscv: fix up struct target_ucontext definition
,
Alistair Francis
,
14:13
Re: [PATCH] roms: opensbi: Upgrade from v0.6 to v0.7
,
Alistair Francis
,
13:44
Re: [PATCH] roms: opensbi: Upgrade from v0.6 to v0.7
,
Alistair Francis
,
13:44
Re: [PATCH] roms: opensbi: Upgrade from v0.6 to v0.7
,
Bin Meng
,
09:20
Re: [PATCH] roms: opensbi: Upgrade from v0.6 to v0.7
,
Philippe Mathieu-Daudé
,
06:05
Re: [PATCH] roms: opensbi: Upgrade from v0.6 to v0.7
,
Bin Meng
,
05:51
Re: [PATCH] roms: opensbi: Upgrade from v0.6 to v0.7
,
Philippe Mathieu-Daudé
,
04:15
Re: [PATCH] linux-user/riscv: fix up struct target_ucontext definition
,
Richard Henderson
,
00:10
April 21, 2020
Re: [PATCH] linux-user/riscv: fix up struct target_ucontext definition
,
LIU Zhiwei
,
22:34
Re: [PATCH] roms: opensbi: Upgrade from v0.6 to v0.7
,
Bin Meng
,
21:30
Re: [PULL] RISC-V Patches for 5.0-rc4
,
Palmer Dabbelt
,
15:33
Re: [PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs
,
Alistair Francis
,
15:29
Re: [PULL] RISC-V Patches for 5.0-rc4
,
Peter Maydell
,
15:28
[PULL 4/6] riscv/sifive_u: Fix up file ordering
,
Palmer Dabbelt
,
15:19
[PULL 6/6] riscv/sifive_u: Add a serial property to the sifive_u machine
,
Palmer Dabbelt
,
15:19
[PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Palmer Dabbelt
,
15:19
[PULL 3/6] riscv: AND stage-1 and stage-2 protection flags
,
Palmer Dabbelt
,
15:19
[PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs
,
Palmer Dabbelt
,
15:19
[PULL 2/6] riscv: Don't use stage-2 PTE lookup protection flags
,
Palmer Dabbelt
,
15:19
[PULL] RISC-V Patches for 5.0-rc4
,
Palmer Dabbelt
,
15:19
Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
,
Palmer Dabbelt
,
13:54
Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
,
Alistair Francis
,
13:48
April 20, 2020
Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
,
Bin Meng
,
22:17
Re: [PATCH] roms: opensbi: Upgrade from v0.6 to v0.7
,
Bin Meng
,
21:34
Re: [PATCH v2 0/2] Support different CPU types for the sifive_e machine
,
Alistair Francis
,
15:31
Re: [PATCH] hw/riscv: Generate correct "mmu-type" for 32-bit machines
,
Alistair Francis
,
15:28
Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
,
Alistair Francis
,
15:26
Re: [PATCH] riscv: Fix Stage2 SV32 page table walk
,
Alistair Francis
,
15:25
Re: [PATCH for 5.0 v1 0/2] RISC-V: Fix Hypervisor guest user space
,
Alistair Francis
,
15:25
Re: [PATCH] roms: opensbi: Upgrade from v0.6 to v0.7
,
Alistair Francis
,
14:41
[PATCH] roms: opensbi: Upgrade from v0.6 to v0.7
,
Bin Meng
,
09:25
April 18, 2020
[PATCH 1/1] target/riscv: fix VS interrupts forwarding to HS
,
Jose Martins
,
14:01
April 17, 2020
Re: [PATCH RFC v2 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Alistair Francis
,
18:43
Re: [PATCH v7 39/61] target/riscv: vector floating-point compare instructions
,
Alistair Francis
,
18:41
Re: [PATCH v7 38/61] target/riscv: vector floating-point sign-injection instructions
,
Alistair Francis
,
18:23
Re: [PATCH v7 36/61] target/riscv: vector floating-point square-root instruction
,
Alistair Francis
,
18:22
Re: [PATCH v7 35/61] target/riscv: vector widening floating-point fused multiply-add instructions
,
Alistair Francis
,
18:19
Re: [PATCH v7 30/61] target/riscv: vector single-width floating-point add/subtract instructions
,
Alistair Francis
,
18:16
Re: [PATCH v7 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions
,
Alistair Francis
,
18:11
Re: [PATCH v7 31/61] target/riscv: vector widening floating-point add/subtract instructions
,
Alistair Francis
,
18:09
Re: [PATCH v7 28/61] target/riscv: vector single-width scaling shift instructions
,
Alistair Francis
,
18:03
Re: [PATCH v7 33/61] target/riscv: vector widening floating-point multiply
,
Alistair Francis
,
17:55
Re: [PATCH v7 29/61] target/riscv: vector narrowing fixed-point clip instructions
,
Alistair Francis
,
17:54
April 15, 2020
Re: [PATCH-for-5.1 v3 18/24] hw/pci-host/pnv_phb3: Move some code from realize() to init()
,
Cédric Le Goater
,
03:52
Re: [PATCH-for-5.1 v3 05/24] hw/arm/aspeed_ast2600: Move some code from realize() to init()
,
Cédric Le Goater
,
03:51
Re: [PATCH-for-5.1 v3 02/24] scripts/coccinelle: Script to simplify DeviceClass error propagation
,
Philippe Mathieu-Daudé
,
02:17
April 14, 2020
Re: [PATCH-for-5.1] gdbstub: Rename GByteArray variable 'mem_buf' as 'array'
,
David Gibson
,
22:19
Re: [PATCH-for-5.1] gdbstub: Rename GByteArray variable 'mem_buf' as 'array'
,
Aleksandar Markovic
,
13:15
Re: [PATCH-for-5.1] gdbstub: Rename GByteArray variable 'mem_buf' as 'array'
,
Aleksandar Markovic
,
13:11
Re: [PATCH-for-5.1] gdbstub: Rename GByteArray variable 'mem_buf' as 'array'
,
Alex Bennée
,
13:06
Re: [PATCH-for-5.1] gdbstub: Rename GByteArray variable 'mem_buf' as 'array'
,
Philippe Mathieu-Daudé
,
12:11
Re: [PATCH-for-5.1 v3 01/23] scripts/coccinelle: Catch missing error_propagate() calls in realize()
,
Markus Armbruster
,
09:25
Re: [PATCH-for-5.1 v3 02/24] scripts/coccinelle: Script to simplify DeviceClass error propagation
,
Markus Armbruster
,
09:17
Re: [PATCH-for-5.1 v3 01/23] scripts/coccinelle: Catch missing error_propagate() calls in realize()
,
Markus Armbruster
,
08:40
Re: [PATCH-for-5.1 v3 02/24] scripts/coccinelle: Script to simplify DeviceClass error propagation
,
Philippe Mathieu-Daudé
,
08:30
Re: [PATCH-for-5.1 v3 02/24] scripts/coccinelle: Script to simplify DeviceClass error propagation
,
Markus Armbruster
,
08:24
Re: [PATCH-for-5.1] gdbstub: Rename GByteArray variable 'mem_buf' as 'array'
,
Philippe Mathieu-Daudé
,
07:35
[PATCH-for-5.1] gdbstub: Rename GByteArray variable 'mem_buf' as 'array'
,
Philippe Mathieu-Daudé
,
07:29
April 13, 2020
Re: hyp v0.6 work?
,
Anup Patel
,
23:53
Re: [PATCH-for-5.1 v3 11/23] hw/pci-host/pnv_phb3: Add missing error-propagation code
,
David Gibson
,
22:32
Re: [PATCH-for-5.1 v3 18/24] hw/pci-host/pnv_phb3: Move some code from realize() to init()
,
David Gibson
,
22:31
Re: [PATCH-for-5.1 v3 01/24] various: Remove suspicious '\' character outside of #define in C code
,
David Gibson
,
22:30
Re: [PATCH-for-5.1 v3 19/24] hw/riscv/sifive_e: Move some code from realize() to init()
,
Alistair Francis
,
18:29
Re: [PATCH-for-5.1 v3 17/24] hw/microblaze/xlnx-zynqmp-pmu: Move some code from realize() to init()
,
Alistair Francis
,
18:28
Re: [PATCH-for-5.1 v3 21/24] hw/riscv/sifive_u: Move some code from realize() to init()
,
Alistair Francis
,
18:24
Re: [PATCH-for-5.1 v3 23/24] hw/riscv/sifive_u: Move some code from realize() to init()
,
Alistair Francis
,
18:24
Re: [PATCH-for-5.1 v3 22/24] hw/riscv/sifive_u: Store MemoryRegion in SiFiveUSoCState
,
Alistair Francis
,
18:23
Re: [PATCH-for-5.1 v3 24/24] hw/riscv/sifive_u: Rename MachineClass::init()
,
Alistair Francis
,
18:22
Re: [PATCH-for-5.1 v3 10/23] hw/microblaze/xlnx-zynqmp-pmu: Add missing error-propagation code
,
Alistair Francis
,
18:22
Re: [PATCH-for-5.1 v3 07/23] hw/riscv/sifive: Add missing error-propagation code
,
Alistair Francis
,
18:20
Re: [PATCH-for-5.1 v3 08/23] hw/arm/armv7m: Add missing error-propagation code
,
Alistair Francis
,
18:19
Re: [PATCH-for-5.1 v3 20/24] hw/riscv/sifive_u: Use single type_init()
,
Alistair Francis
,
18:18
Re: [PATCH-for-5.1 v3 16/24] hw/arm/xlnx-zynqmp: Move some code from realize() to init()
,
Alistair Francis
,
18:15
Re: [PATCH-for-5.1 v3 14/24] hw/arm/xlnx-zynqmp: Use single propagate_error() call
,
Alistair Francis
,
18:13
Re: [PATCH-for-5.1 v3 13/24] hw/arm/stm32f205_soc: Move some code from realize() to init()
,
Alistair Francis
,
18:10
Re: [PATCH-for-5.1 v3 12/24] hw/arm/stm32f205_soc: Store MemoryRegion in STM32F205State
,
Alistair Francis
,
18:09
Re: [PATCH-for-5.1 v3 11/24] hw/arm/msf2-soc: Store MemoryRegion in MSF2State
,
Alistair Francis
,
18:08
Re: [PATCH-for-5.1 v3 03/24] hw/arm/allwinner-a10: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
17:02
Re: [PATCH-for-5.1 v3 06/23] hw/arm/msf2-soc: Add missing error-propagation code
,
Alistair Francis
,
12:05
Re: [PATCH-for-5.1 v3 01/24] various: Remove suspicious '\' character outside of #define in C code
,
Alistair Francis
,
12:04
hyp v0.6 work?
,
Jose Martins
,
11:31
April 12, 2020
Re: [PATCH-for-5.1 v3 00/23] various: Fix error-propagation with Coccinelle scripts (part 2)
,
no-reply
,
21:32
Re: [PATCH-for-5.1 v3 00/24] various: Fix error-propagation with Coccinelle scripts (part 1)
,
no-reply
,
20:41
[PATCH-for-5.1 v3 0/7] various: Fix error-propagation with Coccinelle scripts (part 3)
,
Philippe Mathieu-Daudé
,
18:45
[PATCH-for-5.1 v3 23/23] hw/sd/milkymist-memcard: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:43
[PATCH-for-5.1 v3 22/23] hw/riscv/sifive_u: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:43
[PATCH-for-5.1 v3 21/23] hw/net/xilinx_axienet: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:43
[PATCH-for-5.1 v3 20/23] hw/misc/macio/macio: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:43
[PATCH-for-5.1 v3 19/23] hw/mips/cps: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:43
[PATCH-for-5.1 v3 18/23] hw/i386/x86: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:43
[PATCH-for-5.1 v3 17/23] hw/dma/xilinx_axidma: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:43
[PATCH-for-5.1 v3 16/23] hw/arm/stm32fx05_soc: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:43
[PATCH-for-5.1 v3 15/23] hw/arm/fsl-imx: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 14/23] hw/arm/bcm2835_peripherals: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 13/23] scripts/coccinelle: Add script to catch missing error_propagate() calls
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 12/23] hw/block/onenand: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 10/23] hw/microblaze/xlnx-zynqmp-pmu: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 11/23] hw/pci-host/pnv_phb3: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 09/23] hw/intc/arm_gicv3_its_kvm: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 08/23] hw/arm/armv7m: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 07/23] hw/riscv/sifive: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 06/23] hw/arm/msf2-soc: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 05/23] hw/arm/allwinner-a10: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 04/23] hw/arm/aspeed: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 03/23] hw/arm/stm32f*05_soc: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 02/23] hw/arm/fsl-imx: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 01/23] scripts/coccinelle: Catch missing error_propagate() calls in realize()
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 00/23] various: Fix error-propagation with Coccinelle scripts (part 2)
,
Philippe Mathieu-Daudé
,
18:42
[PATCH-for-5.1 v3 24/24] hw/riscv/sifive_u: Rename MachineClass::init()
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 23/24] hw/riscv/sifive_u: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 22/24] hw/riscv/sifive_u: Store MemoryRegion in SiFiveUSoCState
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 21/24] hw/riscv/sifive_u: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 20/24] hw/riscv/sifive_u: Use single type_init()
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 19/24] hw/riscv/sifive_e: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 18/24] hw/pci-host/pnv_phb3: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 17/24] hw/microblaze/xlnx-zynqmp-pmu: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 16/24] hw/arm/xlnx-zynqmp: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 15/24] hw/arm/xlnx-zynqmp: Split xlnx_zynqmp_create_rpu() as init + realize
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 14/24] hw/arm/xlnx-zynqmp: Use single propagate_error() call
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 13/24] hw/arm/stm32f205_soc: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 12/24] hw/arm/stm32f205_soc: Store MemoryRegion in STM32F205State
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 11/24] hw/arm/msf2-soc: Store MemoryRegion in MSF2State
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 10/24] hw/arm/fsl-imx31: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 09/24] hw/arm/fsl-imx6: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 08/24] hw/arm/fsl-imx6: Simplify checks on 'smp_cpus' count
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 07/24] hw/arm/aspeed_soc: Simplify use of Error*
,
Philippe Mathieu-Daudé
,
18:37
[PATCH-for-5.1 v3 06/24] hw/arm/aspeed_soc: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:36
[PATCH-for-5.1 v3 05/24] hw/arm/aspeed_ast2600: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:36
[PATCH-for-5.1 v3 04/24] hw/arm/aspeed_ast2600: Simplify use of Error*
,
Philippe Mathieu-Daudé
,
18:36
[PATCH-for-5.1 v3 01/24] various: Remove suspicious '\' character outside of #define in C code
,
Philippe Mathieu-Daudé
,
18:36
[PATCH-for-5.1 v3 03/24] hw/arm/allwinner-a10: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
18:36
[PATCH-for-5.1 v3 02/24] scripts/coccinelle: Script to simplify DeviceClass error propagation
,
Philippe Mathieu-Daudé
,
18:36
[PATCH-for-5.1 v3 00/24] various: Fix error-propagation with Coccinelle scripts (part 1)
,
Philippe Mathieu-Daudé
,
18:36
April 11, 2020
[PATCH] linux-user/riscv: fix up struct target_ucontext definition
,
LIU Zhiwei
,
22:08
Re: [PATCH RFC v2 0/9] Add riscv kvm accel support
,
no-reply
,
01:48
[PATCH RFC v2 3/9] target/riscv: Implement function kvm_arch_init_vcpu
,
Yifei Jiang
,
00:17
[PATCH RFC v2 1/9] linux-header: Update linux/kvm.h
,
Yifei Jiang
,
00:17
[PATCH RFC v2 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
,
Yifei Jiang
,
00:16
[PATCH RFC v2 6/9] target/riscv: Support start kernel directly by KVM
,
Yifei Jiang
,
00:16
[PATCH RFC v2 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
,
Yifei Jiang
,
00:16
[PATCH RFC v2 4/9] target/riscv: Implement kvm_arch_get_registers
,
Yifei Jiang
,
00:16
[PATCH RFC v2 9/9] target/riscv: add host cpu type
,
Yifei Jiang
,
00:16
[PATCH RFC v2 5/9] target/riscv: Implement kvm_arch_put_registers
,
Yifei Jiang
,
00:16
[PATCH RFC v2 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Yifei Jiang
,
00:16
[PATCH RFC v2 0/9] Add riscv kvm accel support
,
Yifei Jiang
,
00:16
RE: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Jiangyifei
,
00:11
April 07, 2020
Re: [PATCH-for-5.1 v2 49/54] various: Use &error_abort in instance_init()
,
Cornelia Huck
,
09:28
Re: [PATCH-for-5.1 v2 49/54] various: Use &error_abort in instance_init()
,
Cédric Le Goater
,
04:59
April 06, 2020
Re: [PATCH-for-5.1 v2 49/54] various: Use &error_abort in instance_init()
,
Philippe Mathieu-Daudé
,
14:20
Re: [PATCH-for-5.1 v2 01/54] various: Remove suspicious '\' character outside of #define in C code
,
Marc-André Lureau
,
13:58
[PATCH-for-5.1 v2 49/54] various: Use &error_abort in instance_init()
,
Philippe Mathieu-Daudé
,
13:49
[PATCH-for-5.1 v2 46/54] hw/riscv/sifive_u: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
13:49
[PATCH-for-5.1 v2 31/54] hw/riscv/sifive: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
13:48
[PATCH-for-5.1 v2 24/54] hw/riscv/sifive_u: Rename MachineClass::init()
,
Philippe Mathieu-Daudé
,
13:48
[PATCH-for-5.1 v2 23/54] hw/riscv/sifive_u: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
13:48
[PATCH-for-5.1 v2 22/54] hw/riscv/sifive_u: Store MemoryRegion in SiFiveUSoCState
,
Philippe Mathieu-Daudé
,
13:48
[PATCH-for-5.1 v2 19/54] hw/riscv/sifive_e: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
13:48
[PATCH-for-5.1 v2 21/54] hw/riscv/sifive_u: Move some code from realize() to init()
,
Philippe Mathieu-Daudé
,
13:48
[PATCH-for-5.1 v2 20/54] hw/riscv/sifive_u: Use single type_init()
,
Philippe Mathieu-Daudé
,
13:48
[PATCH-for-5.1 v2 01/54] various: Remove suspicious '\' character outside of #define in C code
,
Philippe Mathieu-Daudé
,
13:48
Re: [PATCH-for-5.0 00/12] hw: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
13:47
Re: [PATCH v2 0/2] Support different CPU types for the sifive_e machine
,
Corey Wharton
,
13:20
Re: [PATCH] riscv: Add semihosting support [v5]
,
Keith Packard
,
01:25
April 05, 2020
Re: [PATCH] hw/riscv: Generate correct "mmu-type" for 32-bit machines
,
Bin Meng
,
09:28
April 04, 2020
Re: [PATCH-for-5.0 00/12] hw: Add missing error-propagation code
,
Markus Armbruster
,
01:56
April 03, 2020
Re: [PATCH-for-5.0 00/12] hw: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
13:53
Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
,
Palmer Dabbelt
,
12:01
April 02, 2020
Re: [PATCH v7 27/61] target/riscv: vector widening saturating scaled multiply-add
,
Alistair Francis
,
19:01
Re: [PATCH v7 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
,
Alistair Francis
,
13:34
Re: [PATCH v7 25/61] target/riscv: vector single-width averaging add and subtract
,
Alistair Francis
,
13:31
Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
,
Bin Meng
,
01:39
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