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[PATCH v1 15/15] target/riscv: Support the v0.6 Hypervisor extension CRS
From: |
Alistair Francis |
Subject: |
[PATCH v1 15/15] target/riscv: Support the v0.6 Hypervisor extension CRSs |
Date: |
Sat, 25 Apr 2020 03:50:52 -0700 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8a145e0a32..690f327828 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -182,9 +182,12 @@
#define CSR_HIDELEG 0x603
#define CSR_HIE 0x604
#define CSR_HCOUNTEREN 0x606
+#define CSR_HGEIE 0x607
#define CSR_HTVAL 0x643
+#define CSR_HVIP 0x645
#define CSR_HIP 0x644
#define CSR_HTINST 0x64A
+#define CSR_HGEIP 0xE12
#define CSR_HGATP 0x680
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 04f3471f2e..3eb6ddd061 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -901,12 +901,25 @@ static int write_hideleg(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
+{
+ int ret = rmw_mip(env, 0, ret_value, new_value,
+ write_mask & hip_writable_mask);
+
+ *ret_value &= hip_writable_mask;
+
+ return ret;
+}
+
static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
int ret = rmw_mip(env, 0, ret_value, new_value,
write_mask & hip_writable_mask);
+ *ret_value &= hip_writable_mask;
+
return ret;
}
@@ -934,6 +947,18 @@ static int write_hcounteren(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
+static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->htval;
@@ -957,6 +982,18 @@ static int write_htinst(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
+static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->hgatp;
@@ -1356,11 +1393,14 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus
},
[CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg
},
[CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg
},
+ [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip
},
[CSR_HIP] = { hmode, NULL, NULL, rmw_hip
},
[CSR_HIE] = { hmode, read_hie, write_hie
},
[CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren
},
+ [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie
},
[CSR_HTVAL] = { hmode, read_htval, write_htval
},
[CSR_HTINST] = { hmode, read_htinst, write_htinst
},
+ [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip
},
[CSR_HGATP] = { hmode, read_hgatp, write_hgatp
},
[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta
},
#if defined(TARGET_RISCV32)
--
2.26.2
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