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[PATCH v1 7/9] riscv/opentitan: Connect the PLIC device
From: |
Alistair Francis |
Subject: |
[PATCH v1 7/9] riscv/opentitan: Connect the PLIC device |
Date: |
Sat, 25 Apr 2020 04:29:25 -0700 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/opentitan.c | 19 +++++++++++++++++--
include/hw/riscv/opentitan.h | 3 +++
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 1f9f4a8dd0..3a845fbb7b 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -25,6 +25,7 @@
#include "hw/misc/unimp.h"
#include "hw/riscv/boot.h"
#include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
static const struct MemmapEntry {
hwaddr base;
@@ -92,6 +93,9 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
object_initialize_child(obj, "cpus", &s->cpus,
sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
&error_abort, NULL);
+
+ sysbus_init_child_obj(obj, "plic", &s->plic,
+ sizeof(s->plic), TYPE_IBEX_PLIC);
}
static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -100,6 +104,9 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState
*dev_soc, Error **errp)
MachineState *ms = MACHINE(qdev_get_machine());
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
MemoryRegion *sys_mem = get_system_memory();
+ DeviceState *dev;
+ SysBusDevice *busdev;
+ Error *err = NULL;
object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
&error_abort);
@@ -120,6 +127,16 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState
*dev_soc, Error **errp)
memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base,
&s->flash_mem);
+ /* PLIC */
+ dev = DEVICE(&s->plic);
+ object_property_set_bool(OBJECT(&s->plic), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, memmap[IBEX_PLIC].base);
+
create_unimplemented_device("riscv.lowrisc.ibex.uart",
memmap[IBEX_UART].base, memmap[IBEX_UART].size);
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
@@ -134,8 +151,6 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState
*dev_soc, Error **errp)
memmap[IBEX_AES].base, memmap[IBEX_AES].size);
create_unimplemented_device("riscv.lowrisc.ibex.hmac",
memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size);
- create_unimplemented_device("riscv.lowrisc.ibex.plic",
- memmap[IBEX_PLIC].base, memmap[IBEX_PLIC].size);
create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size);
create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 15a3d87ed0..8d6a09b696 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -20,6 +20,7 @@
#define HW_OPENTITAN_H
#include "hw/riscv/riscv_hart.h"
+#include "hw/intc/ibex_plic.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
#define RISCV_IBEX_SOC(obj) \
@@ -31,6 +32,8 @@ typedef struct LowRISCIbexSoCState {
/*< public >*/
RISCVHartArrayState cpus;
+ IbexPlicState plic;
+
MemoryRegion flash_mem;
MemoryRegion rom;
} LowRISCIbexSoCState;
--
2.26.2
- [PATCH v1 0/9] RISC-V Add the OpenTitan Machine, Alistair Francis, 2020/04/26
- [PATCH v1 1/9] riscv/boot: Add a missing header include, Alistair Francis, 2020/04/26
- [PATCH v1 2/9] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/04/26
- [PATCH v1 3/9] target/riscv: Add the lowRISC Ibex CPU, Alistair Francis, 2020/04/26
- [PATCH v1 5/9] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/04/26
- [PATCH v1 4/9] riscv: Initial commit of OpenTitan machine, Alistair Francis, 2020/04/26
- [PATCH v1 8/9] riscv/opentitan: Connect the UART device, Alistair Francis, 2020/04/26
- [PATCH v1 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/04/26
- [PATCH v1 9/9] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/04/26
- [PATCH v1 7/9] riscv/opentitan: Connect the PLIC device,
Alistair Francis <=