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[PULL 10/14] linux-user/riscv: fix up struct target_ucontext definition
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From: |
Alistair Francis |
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Subject: |
[PULL 10/14] linux-user/riscv: fix up struct target_ucontext definition |
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Date: |
Wed, 29 Apr 2020 11:28:52 -0700 |
From: LIU Zhiwei <address@hidden>
As struct target_ucontext will be transfered to signal handler, it
must keep pace with struct ucontext_t defined in Linux kernel.
Signed-off-by: LIU Zhiwei <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
linux-user/riscv/signal.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
index 83ecc6f799..67a95dbc7b 100644
--- a/linux-user/riscv/signal.c
+++ b/linux-user/riscv/signal.c
@@ -40,8 +40,9 @@ struct target_ucontext {
unsigned long uc_flags;
struct target_ucontext *uc_link;
target_stack_t uc_stack;
- struct target_sigcontext uc_mcontext;
target_sigset_t uc_sigmask;
+ uint8_t __unused[1024 / 8 - sizeof(target_sigset_t)];
+ struct target_sigcontext uc_mcontext QEMU_ALIGNED(16);
};
struct target_rt_sigframe {
--
2.26.2
- [PULL 00/14] RISC-V Patch Queue for 5.1, Alistair Francis, 2020/04/29
- [PULL 01/14] riscv/sifive_u: Fix up file ordering, Alistair Francis, 2020/04/29
- [PULL 02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/04/29
- [PULL 06/14] riscv: Fix Stage2 SV32 page table walk, Alistair Francis, 2020/04/29
- [PULL 05/14] riscv: AND stage-1 and stage-2 protection flags, Alistair Francis, 2020/04/29
- [PULL 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine, Alistair Francis, 2020/04/29
- [PULL 04/14] riscv: Don't use stage-2 PTE lookup protection flags, Alistair Francis, 2020/04/29
- [PULL 10/14] linux-user/riscv: fix up struct target_ucontext definition,
Alistair Francis <=
- [PULL 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines, Alistair Francis, 2020/04/29
- [PULL 08/14] riscv: sifive_e: Support changing CPU type, Alistair Francis, 2020/04/29
- [PULL 09/14] target/riscv: Add a sifive-e34 cpu type, Alistair Francis, 2020/04/29
- [PULL 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware(), Alistair Francis, 2020/04/29
- [PULL 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option, Alistair Francis, 2020/04/29
- [PULL 14/14] hw/riscv/spike: Allow more than one CPUs, Alistair Francis, 2020/04/29
- [PULL 11/14] roms: opensbi: Upgrade from v0.6 to v0.7, Alistair Francis, 2020/04/29
- Re: [PULL 00/14] RISC-V Patch Queue for 5.1, Peter Maydell, 2020/04/29