[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 01/17] target/riscv: Set access as data_load when validating s
From: |
Alistair Francis |
Subject: |
[PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs |
Date: |
Thu, 4 Jun 2020 18:20:45 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 62fe1ecc8f..eda7057663 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -435,7 +435,7 @@ restart:
hwaddr vbase;
/* Do the second stage translation on the base PTE address. */
- get_physical_address(env, &vbase, &vbase_prot, base, access_type,
+ get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD,
mmu_idx, false, true);
pte_addr = vbase + idx * ptesize;
--
2.26.2
- [PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1, Alistair Francis, 2020/06/04
- [PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs,
Alistair Francis <=
- [PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/04
- [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/04
- [PATCH v2 04/17] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/04
- [PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/06/04
- [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/06/04
- [PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/06/04