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[PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the v
From: |
Alistair Francis |
Subject: |
[PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status |
Date: |
Thu, 4 Jun 2020 18:20:56 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 18 ++++++++++++++++++
3 files changed, 21 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 80569f0d44..93ae472490 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -295,6 +295,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
+bool riscv_cpu_two_stage_lookup(CPURISCVState *env);
+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7f64ee1174..f52711ac32 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -452,6 +452,7 @@
* page table fault.
*/
#define FORCE_HS_EXCEP 2
+#define HS_TWO_STAGE 4
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 75d2ae3434..68abccc993 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -220,6 +220,24 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool
enable)
env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
}
+bool riscv_cpu_two_stage_lookup(CPURISCVState *env)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return false;
+ }
+
+ return get_field(env->virt, HS_TWO_STAGE);
+}
+
+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ env->virt = set_field(env->virt, HS_TWO_STAGE, enable);
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
--
2.26.2
- [PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1, Alistair Francis, 2020/06/04
- [PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/06/04
- [PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/04
- [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/04
- [PATCH v2 04/17] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/04
- [PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status,
Alistair Francis <=
- [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/06/04
- [PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/06/04
- [PATCH v2 07/17] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 08/17] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/06/04
- [PATCH v2 09/17] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/06/04
- [PATCH v2 13/17] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/06/04
- [PATCH v2 10/17] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/06/04
- [PATCH v2 14/17] target/riscv: Only support little endian guests, Alistair Francis, 2020/06/04
- [PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/06/04