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[PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support
From: |
Bin Meng |
Subject: |
[PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support |
Date: |
Mon, 15 Jun 2020 17:50:36 -0700 |
From: Bin Meng <bin.meng@windriver.com>
This series updates the 'sifive_u' machine support:
- Change SiFive E/U series CPU reset vector to 0x1004
- Support Mode Select (MSEL[3:0]) settings at 0x1000 via a new
"msel" machine property
- Add a dummy DDR memory controller device
With this series, QEMU can boot U-Boot SPL built for SiFive FU540
all the way up to loading U-Boot proper from MMC:
$ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin
U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
Trying to boot from MMC1
Unhandled exception: Load access fault
EPC: 0000000008009be6 TVAL: 0000000010050014
The last big gap for the 'sifive_u' machine is the QSPI modeling.
Changes in v2:
- Drop the already applied patch 01 to 11 in v1
- new patch: Rename IBEX CPU init routine
- rebase on https://github.com/alistair23/qemu riscv-to-apply.next branch
- rename SiFive E/U CPU init routine names
Bin Meng (5):
target/riscv: Rename IBEX CPU init routine
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
hw/riscv: sifive_u: Support different boot source per MSEL pin state
hw/riscv: sifive_u: Sort the SoC memmap table entries
hw/riscv: sifive_u: Add a dummy DDR memory controller device
hw/riscv/sifive_e.c | 10 +++++----
hw/riscv/sifive_u.c | 51 ++++++++++++++++++++++++++++++++++-----------
include/hw/riscv/sifive_u.h | 7 +++++++
target/riscv/cpu.c | 20 +++++++++---------
4 files changed, 62 insertions(+), 26 deletions(-)
--
2.7.4
- [PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support,
Bin Meng <=
[PATCH v2 4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries, Bin Meng, 2020/06/15
[PATCH v2 3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Bin Meng, 2020/06/15