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Re: [PATCH v2 1/5] target/riscv: Rename IBEX CPU init routine
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 1/5] target/riscv: Rename IBEX CPU init routine |
Date: |
Tue, 16 Jun 2020 10:07:29 -0700 |
On Mon, Jun 15, 2020 at 5:51 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Current IBEX CPU init routine name seems to be too generic.
> Since it uses a different reset vector from the generic one,
> it merits a dedicated name.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> Changes in v2:
> - new patch: Rename IBEX CPU init routine
>
> target/riscv/cpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e867766..5f03458 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -153,7 +153,7 @@ static void rvxx_imacu_nommu_cpu_init(Object *obj)
>
> #if defined(TARGET_RISCV32)
>
> -static void rv32_imcu_nommu_cpu_init(Object *obj)
> +static void rv32_ibex_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV32 | RVI | RVM | RVC | RVU);
> @@ -577,7 +577,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> #if defined(TARGET_RISCV32)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_imcu_nommu_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,
> rvxx_gcsu_priv1_10_0_cpu_init),
> --
> 2.7.4
>
>
[PATCH v2 4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries, Bin Meng, 2020/06/15
[PATCH v2 3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Bin Meng, 2020/06/15
[PATCH v2 5/5] hw/riscv: sifive_u: Add a dummy DDR memory controller device, Bin Meng, 2020/06/15
Re: [PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support, Alistair Francis, 2020/06/16