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[PATCH 0/2] target/riscv: fixup atomic implementation
From: |
LIU Zhiwei |
Subject: |
[PATCH 0/2] target/riscv: fixup atomic implementation |
Date: |
Mon, 29 Jun 2020 21:07:29 +0800 |
When I tested RVA with RISU, I found there is something wrong.
In particular, amo*.w instructions should only operate the lowerest 32
bits. However, the current implementation uses the whole XLEN bits.
LIU Zhiwei (2):
tcg/tcg-op: Fix nonatomic_op load with MO_SIGN
target/riscv: Do amo*.w insns operate with 32 bits
target/riscv/insn_trans/trans_rva.inc.c | 60 +++++++++++++++++++------
tcg/tcg-op.c | 4 +-
2 files changed, 49 insertions(+), 15 deletions(-)
--
2.23.0
- [PATCH 0/2] target/riscv: fixup atomic implementation,
LIU Zhiwei <=