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Re: [PATCH 2/2] target/riscv: Do amo*.w insns operate with 32 bits
From: |
Richard Henderson |
Subject: |
Re: [PATCH 2/2] target/riscv: Do amo*.w insns operate with 32 bits |
Date: |
Tue, 30 Jun 2020 08:00:59 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 6/29/20 6:07 AM, LIU Zhiwei wrote:
> +static bool
> +gen_amo_w(DisasContext *ctx, arg_atomic *a,
> + void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
> + MemOp mop, bool sign)
> {
> TCGv src1 = tcg_temp_new();
> TCGv src2 = tcg_temp_new();
>
> gen_get_gpr(src1, a->rs1);
> gen_get_gpr(src2, a->rs2);
> + if (sign) {
> + tcg_gen_ext32s_tl(src2, src2);
> + } else {
> + tcg_gen_ext32u_tl(src2, src2);
> + }
>
> (*func)(src2, src1, src2, ctx->mem_idx, mop);
> -
> + tcg_gen_ext32s_tl(src2, src2);
> gen_set_gpr(a->rd, src2);
> +
> tcg_temp_free(src1);
> tcg_temp_free(src2);
> return true;
With the fix to tcg, there should be no change required here, since you're
already passing MO_TESL for signed input.
Note that unsigned comparisions work as expected with sign-extended inputs.
That's what the risc-v isa does, after all.
r~