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qemu-riscv (date)
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Last Modified: Fri Jul 31 2020 13:30:52 -0400
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July 31, 2020
Re: [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions
,
Richard Henderson
,
13:30
Re: [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64
,
Richard Henderson
,
13:25
Re: [RFC v2 72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
,
Richard Henderson
,
13:18
Re: [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert
,
Richard Henderson
,
13:10
Re: [RFC v2 67/76] target/riscv: rvv-0.9: remove integer extract instruction
,
Richard Henderson
,
13:05
Re: [RFC v2 66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
,
Richard Henderson
,
13:03
Re: [RFC v2 65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
,
Richard Henderson
,
13:02
Re: [RFC v2 64/76] target/riscv: rvv-0.9: single-width scaling shift instructions
,
Richard Henderson
,
13:00
Re: [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction
,
Richard Henderson
,
12:45
Re: [RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions
,
Richard Henderson
,
12:32
Re: [RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions
,
Richard Henderson
,
12:07
Re: [RFC v2 59/76] target/riscv: rvv-0.9: floating-point slide instructions
,
Richard Henderson
,
12:05
Re: [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions
,
Richard Henderson
,
11:57
Re: [RFC v2 56/76] target/riscv: rvv-0.9: widening integer reduction instructions
,
Richard Henderson
,
11:14
Re: [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions
,
Frank Chang
,
06:18
July 30, 2020
[RFC PATCH v2 2/2] hw/riscv: sifive_u: Add write-once protection.
,
Green Wan
,
22:48
[RFC PATCH v2 1/2] hw/riscv: sifive_u: Add file-backed OTP.
,
Green Wan
,
22:47
[RFC PATCH v2 0/2] Add write-once and file-backed features to OTP
,
Green Wan
,
22:47
Re: [RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions
,
Richard Henderson
,
17:32
Re: [RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions
,
Richard Henderson
,
17:31
Re: [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions
,
Richard Henderson
,
17:24
Re: [RFC v2 49/76] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
,
Richard Henderson
,
17:19
Re: [RFC v2 48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions
,
Richard Henderson
,
17:04
Re: [RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions
,
Richard Henderson
,
17:02
Re: [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions
,
Richard Henderson
,
16:47
Re: [RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions
,
Richard Henderson
,
16:45
Re: [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions
,
Richard Henderson
,
16:35
Re: [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions
,
Richard Henderson
,
16:14
Re: [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction
,
Richard Henderson
,
16:05
Re: [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions
,
Richard Henderson
,
16:03
Re: [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction
,
Richard Henderson
,
15:57
Re: [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions
,
Richard Henderson
,
10:50
Re: [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended
,
Richard Henderson
,
09:43
Re: [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction
,
Richard Henderson
,
09:31
Re: [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction
,
Richard Henderson
,
09:29
Re: [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions
,
Richard Henderson
,
09:27
Re: [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction
,
Richard Henderson
,
09:13
Re: [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction
,
Richard Henderson
,
09:05
Re: [RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions
,
Richard Henderson
,
09:02
Re: [RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction
,
Richard Henderson
,
09:02
Re: [RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation
,
Richard Henderson
,
08:53
Re: [RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
,
Richard Henderson
,
08:44
Re: [RFC v2 01/76] target/riscv: drop vector 0.7.1 support
,
Richard Henderson
,
08:27
[PATCH 3/3] softfloat: add fp16 and uint8/int8 interconvert functions
,
Chih-Min Chao
,
05:52
[PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation
,
Chih-Min Chao
,
05:52
[PATCH 1/3] softfloat: target/riscv: implement full set fp16 comparision
,
Chih-Min Chao
,
05:52
[PATCH 0/3] float16 APIs and alternative sNaN handling
,
Chih-Min Chao
,
05:52
Re: [RFC v2 01/76] target/riscv: drop vector 0.7.1 support
,
Frank Chang
,
04:07
July 29, 2020
Re: [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions
,
Richard Henderson
,
16:30
[PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
07:28
[PATCH 2/3] target/riscv: Fix write_htinst() implementation
,
Anup Patel
,
07:28
[PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs
,
Anup Patel
,
07:28
[PATCH 0/3] Trapped instruction encoding support
,
Anup Patel
,
07:28
Re: [PATCH v4 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Bin Meng
,
01:10
Re: [PATCH v4 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Alistair Francis
,
01:05
Re: [PATCH v4 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Bin Meng
,
00:51
July 28, 2020
Re: [PATCH v6 3/4] target/riscv: Fix the translation of physical address
,
Alistair Francis
,
20:06
Re: [PATCH v5 7/7] Makefile: Ship the generic platform bios ELF images for RISC-V
,
Alistair Francis
,
14:27
Re: [PATCH v4 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Alistair Francis
,
14:26
Re: [PATCH v5 7/7] Makefile: Ship the generic platform bios ELF images for RISC-V
,
Bin Meng
,
11:52
Re: [PATCH v4 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Bin Meng
,
11:46
Re: [PATCH v4 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Alistair Francis
,
11:39
Re: [PATCH v5 7/7] Makefile: Ship the generic platform bios ELF images for RISC-V
,
Alistair Francis
,
11:37
Re: [PATCH] hw/riscv: sifive_u: Add a dummy L2 cache controller device
,
Alistair Francis
,
11:33
Re: [RFC PATCH 1/2] hw/riscv: sifive_u: Add file-backed OTP. softmmu/vl: add otp-file to boot option
,
Paolo Bonzini
,
04:28
[PATCH v6 4/4] target/riscv: Change the TLB page size depends on PMP entries.
,
Zong Li
,
04:26
[PATCH v6 3/4] target/riscv: Fix the translation of physical address
,
Zong Li
,
04:26
[PATCH v6 2/4] target/riscv/pmp.c: Fix the index offset on RV64
,
Zong Li
,
04:26
[PATCH v6 1/4] target/riscv: Fix the range of pmpcfg of CSR funcion table
,
Zong Li
,
04:26
[PATCH v6 0/4] Fix some PMP implementations
,
Zong Li
,
04:26
July 27, 2020
Re: [PATCH v5 3/4] target/riscv: Fix the translation of physical address
,
Zong Li
,
22:32
Re: [RFC PATCH 1/2] hw/riscv: sifive_u: Add file-backed OTP. softmmu/vl: add otp-file to boot option
,
Green Wan
,
22:03
Re: [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison
,
Alistair Francis
,
19:48
Re: [PATCH v5 3/4] target/riscv: Fix the translation of physical address
,
Alistair Francis
,
18:49
Re: [PATCH v5 2/4] target/riscv/pmp.c: Fix the index offset on RV64
,
Alistair Francis
,
18:37
Re: [RFC v2 01/76] target/riscv: drop vector 0.7.1 support
,
Alistair Francis
,
16:05
Re: [RFC v2 01/76] target/riscv: drop vector 0.7.1 support
,
Palmer Dabbelt
,
15:54
Re: [PATCH v5 2/4] target/riscv/pmp.c: Fix the index offset on RV64
,
Bin Meng
,
03:06
July 25, 2020
Re: [PATCH v4 2/4] target/riscv/pmp.c: Fix the index offset on RV64
,
Zong Li
,
11:06
[PATCH v5 4/4] target/riscv: Change the TLB page size depends on PMP entries.
,
Zong Li
,
11:03
[PATCH v5 3/4] target/riscv: Fix the translation of physical address
,
Zong Li
,
11:03
[PATCH v5 2/4] target/riscv/pmp.c: Fix the index offset on RV64
,
Zong Li
,
11:03
[PATCH v5 1/4] target/riscv: Fix the range of pmpcfg of CSR funcion table
,
Zong Li
,
11:03
[PATCH v5 0/4] Fix some PMP implementations
,
Zong Li
,
11:03
[PATCH v1 3/3] hw/intc: ibex_plic: Honour source priorities
,
Alistair Francis
,
01:44
[PATCH v1 2/3] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines
,
Alistair Francis
,
01:44
[PATCH v1 1/3] hw/intc: ibex_plic: Update the pending irqs
,
Alistair Francis
,
01:44
[PATCH v1 0/3] hw/intc: A few fixes for the Ibex PLIC
,
Alistair Francis
,
01:44
July 24, 2020
Re: [RFC PATCH 1/2] hw/riscv: sifive_u: Add file-backed OTP. softmmu/vl: add otp-file to boot option
,
Bin Meng
,
10:20
[RFC PATCH 2/2] hw/riscv: sifive_u: Add write-once protection.
,
Green Wan
,
09:54
[RFC PATCH 1/2] hw/riscv: sifive_u: Add file-backed OTP. softmmu/vl: add otp-file to boot option
,
Green Wan
,
09:54
[RFC PATCH 0/2] Add write-once and file-backed features to OTP
,
Green Wan
,
09:54
Re: [PATCH v4 2/4] target/riscv/pmp.c: Fix the index offset on RV64
,
Bin Meng
,
05:22
[PATCH v4 4/4] target/riscv: Change the TLB page size depends on PMP entries.
,
Zong Li
,
05:08
[PATCH v4 3/4] target/riscv: Fix the translation of physical address
,
Zong Li
,
05:08
[PATCH v4 2/4] target/riscv/pmp.c: Fix the index offset on RV64
,
Zong Li
,
05:08
[PATCH v4 1/4] target/riscv: Fix the range of pmpcfg of CSR funcion table
,
Zong Li
,
05:08
[PATCH v4 0/4] Fix some PMP implementations
,
Zong Li
,
05:08
Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers
,
LIU Zhiwei
,
02:05
Re: [PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c
,
LIU Zhiwei
,
02:04
July 23, 2020
Re: [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers
,
Richard Henderson
,
23:59
Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers
,
Richard Henderson
,
23:55
Re: [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers
,
LIU Zhiwei
,
22:47
Re: [PATCH v2 3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c
,
LIU Zhiwei
,
22:41
Re: [PATCH v2 2/7] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
,
LIU Zhiwei
,
22:40
Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers
,
LIU Zhiwei
,
22:35
Re: [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison
,
LIU Zhiwei
,
22:31
[PATCH v2 7/7] target/riscv: check before allocating TCG temps
,
Richard Henderson
,
20:28
[PATCH v2 6/7] target/riscv: Clean up fmv.w.x
,
Richard Henderson
,
20:28
[PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c
,
Richard Henderson
,
20:28
[PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers
,
Richard Henderson
,
20:28
[PATCH v2 3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c
,
Richard Henderson
,
20:28
[PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers
,
Richard Henderson
,
20:28
[PATCH v2 2/7] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
,
Richard Henderson
,
20:28
[PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison
,
Richard Henderson
,
20:28
Re: [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper
,
Richard Henderson
,
12:14
Re: [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper
,
Frank Chang
,
03:13
July 22, 2020
Re: [PATCH v3 3/3] target/riscv: Fix the translation of physical address
,
Zong Li
,
23:20
Re: [PATCH v3 2/3] target/riscv/pmp.c: Fix the index offset on RV64
,
Zong Li
,
23:19
Re: [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA
,
Frank Chang
,
22:18
Re: [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL
,
Frank Chang
,
22:11
Re: [RFC v2 21/76] target/riscv: rvv-0.9: configure instructions
,
Richard Henderson
,
16:00
Re: [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper
,
Richard Henderson
,
15:15
Re: [RFC v2 18/76] target/riscv: introduce more imm value modes in translator functions
,
Richard Henderson
,
14:08
Re: [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA
,
Richard Henderson
,
14:00
Re: [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL
,
Richard Henderson
,
13:30
Re: [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations
,
Richard Henderson
,
13:04
Re: [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register
,
Richard Henderson
,
12:59
Re: [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register
,
Richard Henderson
,
12:57
Re: [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register
,
Richard Henderson
,
12:54
Re: [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status
,
Richard Henderson
,
12:53
Re: [PATCH 1/2] target/riscv: Quiet Coverity complains about vamo*
,
Alistair Francis
,
12:50
Re: [RFC v2 01/76] target/riscv: drop vector 0.7.1 support
,
Alistair Francis
,
12:47
Re: [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field
,
Richard Henderson
,
12:34
Re: [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field
,
Richard Henderson
,
12:33
Re: [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field
,
Richard Henderson
,
12:19
Re: [RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
,
Richard Henderson
,
12:18
Re: [RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9
,
Richard Henderson
,
12:13
Re: [RFC v2 52/76] fpu: implement full set compare for fp16
,
Alex Bennée
,
07:36
[RFC v2 76/76] target/riscv: gdb: support vector registers for rv32
,
frank . chang
,
05:22
[RFC v2 75/76] target/riscv: gdb: support vector registers for rv64
,
frank . chang
,
05:22
[RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map
,
frank . chang
,
05:22
[RFC v2 73/76] fpu: fix float16 nan check
,
frank . chang
,
05:22
[RFC v2 72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
,
frank . chang
,
05:22
[RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert
,
frank . chang
,
05:22
[RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions
,
frank . chang
,
05:22
[RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions
,
frank . chang
,
05:22
[RFC v2 68/76] fpu: add api to handle alternative sNaN propagation
,
frank . chang
,
05:22
[RFC v2 67/76] target/riscv: rvv-0.9: remove integer extract instruction
,
frank . chang
,
05:22
[RFC v2 66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
,
frank . chang
,
05:22
[RFC v2 65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
,
frank . chang
,
05:22
[RFC v2 64/76] target/riscv: rvv-0.9: single-width scaling shift instructions
,
frank . chang
,
05:22
[RFC v2 63/76] target/riscv: rvv-0.9: widening floating-point reduction instructions
,
frank . chang
,
05:22
[RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction
,
frank . chang
,
05:22
[RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions
,
frank . chang
,
05:21
[RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions
,
frank . chang
,
05:21
[RFC v2 59/76] target/riscv: rvv-0.9: floating-point slide instructions
,
frank . chang
,
05:21
[RFC v2 58/76] target/riscv: rvv-0.9: slide instructions
,
frank . chang
,
05:21
[RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions
,
frank . chang
,
05:21
[RFC v2 56/76] target/riscv: rvv-0.9: widening integer reduction instructions
,
frank . chang
,
05:21
[RFC v2 55/76] target/riscv: rvv-0.9: single-width integer reduction instructions
,
frank . chang
,
05:21
[RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions
,
frank . chang
,
05:21
[RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions
,
frank . chang
,
05:21
[RFC v2 52/76] fpu: implement full set compare for fp16
,
frank . chang
,
05:21
[RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions
,
frank . chang
,
05:21
[RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions
,
frank . chang
,
05:21
[RFC v2 49/76] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
,
frank . chang
,
05:21
[RFC v2 48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions
,
frank . chang
,
05:21
[RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions
,
frank . chang
,
05:21
[RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
,
frank . chang
,
05:20
[RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions
,
frank . chang
,
05:20
[RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions
,
frank . chang
,
05:20
[RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions
,
frank . chang
,
05:20
[RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions
,
frank . chang
,
05:20
[RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions
,
frank . chang
,
05:20
[RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction
,
frank . chang
,
05:20
[RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions
,
frank . chang
,
05:20
[RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions
,
frank . chang
,
05:20
[RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended
,
frank . chang
,
05:20
[RFC v2 36/76] target/riscv: rvv-0.9: element index instruction
,
frank . chang
,
05:20
[RFC v2 35/76] target/riscv: rvv-0.9: iota instruction
,
frank . chang
,
05:20
[RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions
,
frank . chang
,
05:20
[RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction
,
frank . chang
,
05:20
[RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction
,
frank . chang
,
05:20
[RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions
,
frank . chang
,
05:19
[RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction
,
frank . chang
,
05:19
[RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation
,
frank . chang
,
05:19
[RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
,
frank . chang
,
05:19
[RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions
,
frank . chang
,
05:19
[RFC v2 26/76] target/riscv: rvv-0.9: amo operations
,
frank . chang
,
05:19
[RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load
,
frank . chang
,
05:19
[RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns
,
frank . chang
,
05:19
[RFC v2 23/76] target/riscv: rvv-0.9: index load and store instructions
,
frank . chang
,
05:19
[RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions
,
frank . chang
,
05:19
[RFC v2 21/76] target/riscv: rvv-0.9: configure instructions
,
frank . chang
,
05:19
[RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans
,
frank . chang
,
05:19
[RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper
,
frank . chang
,
05:18
[RFC v2 18/76] target/riscv: introduce more imm value modes in translator functions
,
frank . chang
,
05:18
[RFC v2 17/76] target/riscv: rvv-0.9: update check functions
,
frank . chang
,
05:18
[RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA
,
frank . chang
,
05:18
[RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL
,
frank . chang
,
05:18
[RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations
,
frank . chang
,
05:18
[RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register
,
frank . chang
,
05:18
[RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register
,
frank . chang
,
05:18
[RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register
,
frank . chang
,
05:18
[RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status
,
frank . chang
,
05:18
[RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field
,
frank . chang
,
05:18
[RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field
,
frank . chang
,
05:18
[RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field
,
frank . chang
,
05:18
[RFC v2 06/76] target/riscv: fix vill bit index in vtype register
,
frank . chang
,
05:17
[RFC v2 05/76] target/riscv: fix return value of do_opivx_widen()
,
frank . chang
,
05:17
[RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
,
frank . chang
,
05:17
[RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
,
frank . chang
,
05:17
[RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9
,
frank . chang
,
05:17
[RFC v2 01/76] target/riscv: drop vector 0.7.1 support
,
frank . chang
,
05:17
[RFC v2 00/76] target/riscv: support vector extension v0.9
,
frank . chang
,
05:17
Re: [PATCH v3 3/3] target/riscv: Fix the translation of physical address
,
Alexander Richardson
,
05:08
Re: [PATCH v3 2/3] target/riscv/pmp.c: Fix the index offset on RV64
,
Bin Meng
,
00:57
July 21, 2020
Re: [PATCH 00/11] RISC-V risu porting
,
LIU Zhiwei
,
22:51
Re: [PATCH 1/2] target/riscv: Quiet Coverity complains about vamo*
,
Peter Maydell
,
11:30
Re: [PATCH] hw/riscv: sifive_e: Correct debug block size
,
Alistair Francis
,
11:22
Re: [PATCH 2/2] target/riscv: fix vector index load/store constraints
,
Alistair Francis
,
11:21
Re: [PATCH 1/2] target/riscv: Quiet Coverity complains about vamo*
,
Alistair Francis
,
11:17
[PATCH 2/2] target/riscv: fix vector index load/store constraints
,
LIU Zhiwei
,
09:38
[PATCH 1/2] target/riscv: Quiet Coverity complains about vamo*
,
LIU Zhiwei
,
09:38
[PATCH v3 3/3] target/riscv: Fix the translation of physical address
,
Zong Li
,
08:41
[PATCH v3 2/3] target/riscv/pmp.c: Fix the index offset on RV64
,
Zong Li
,
08:41
[PATCH v3 1/3] target/riscv: Fix the range of pmpcfg of CSR funcion table
,
Zong Li
,
08:41
[PATCH v3 0/3] Fix some PMP implementation
,
Zong Li
,
08:41
Re: [PATCH v2 2/2] target/riscv/pmp.c: Fix the index offset on RV64
,
Bin Meng
,
02:11
[PATCH v2 2/2] target/riscv/pmp.c: Fix the index offset on RV64
,
Zong Li
,
02:03
[PATCH v2 1/2] target/riscv: Fix the range of pmpcfg of CSR funcion table
,
Zong Li
,
02:03
[PATCH v2 0/2] Fix some PMP implementation
,
Zong Li
,
02:03
July 20, 2020
Re: [PATCH 2/2] target/riscv/pmp.c: Fix the index offset on RV64
,
Zong Li
,
22:46
Re: [PATCH 1/2] target/riscv: Fix the range of pmpcfg of CSR funcion table
,
Bin Meng
,
22:41
Re: [PATCH 2/2] target/riscv/pmp.c: Fix the index offset on RV64
,
Bin Meng
,
22:41
Re: [PATCH 1/2] target/riscv: Fix the range of pmpcfg of CSR funcion table
,
Alistair Francis
,
19:22
Re: [PATCH v2] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
,
Alistair Francis
,
19:21
[PATCH 2/2] target/riscv/pmp.c: Fix the index offset on RV64
,
Zong Li
,
05:44
[PATCH 1/2] target/riscv: Fix the range of pmpcfg of CSR funcion table
,
Zong Li
,
05:44
[PATCH 0/2] Fix some PMP implementation
,
Zong Li
,
05:44
[PATCH] hw/riscv: sifive_u: Add a dummy L2 cache controller device
,
Bin Meng
,
02:50
July 18, 2020
Re: [PATCH v2] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
,
Richard Henderson
,
14:56
Re: [PATCH v2] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
,
Peter Maydell
,
14:09
Re: [PATCH v2] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
,
Jessica Clarke
,
10:44
Re: [PATCH v2] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
,
Philippe Mathieu-Daudé
,
03:43
July 17, 2020
[PATCH v2] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
,
Jessica Clarke
,
20:49
Re: [PATCH] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
,
Richard Henderson
,
20:44
[PATCH] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
,
Jessica Clarke
,
20:22
July 16, 2020
Replacing the existing kernel image with new image
,
Pankaj Vinadrao Joshi
,
09:28
Re: [PATCH] hw/riscv: sifive_e: Correct debug block size
,
no-reply
,
05:52
[PATCH] hw/riscv: sifive_e: Correct debug block size
,
Bin Meng
,
05:31
Re: [PATCH for-5.1 1/2] msf2: Unbreak device-list-properties for "msf-soc"
,
sundeep subbaraya
,
03:54
Re: [PATCH for-5.1 1/2] msf2: Unbreak device-list-properties for "msf-soc"
,
Philippe Mathieu-Daudé
,
03:36
Re: [PATCH for-5.1 1/2] msf2: Unbreak device-list-properties for "msf-soc"
,
Thomas Huth
,
02:07
[PATCH v5 7/7] Makefile: Ship the generic platform bios ELF images for RISC-V
,
Bin Meng
,
01:56
[PATCH v5 6/7] gitlab-ci/opensbi: Update GitLab CI to build generic platform
,
Bin Meng
,
01:56
[PATCH v5 5/7] hw/riscv: spike: Change the default bios to use generic platform image
,
Bin Meng
,
01:56
[PATCH v5 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Bin Meng
,
01:56
[PATCH v5 2/7] roms/opensbi: Upgrade from v0.7 to v0.8
,
Bin Meng
,
01:56
[PATCH v5 3/7] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware
,
Bin Meng
,
01:56
[PATCH v5 0/7] riscv: Switch to use generic platform fw_dynamic type opensbi bios images
,
Bin Meng
,
01:56
[PATCH v5 1/7] configure: Create symbolic links for pc-bios/*.elf files
,
Bin Meng
,
01:56
Re: [PATCH v4 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Bin Meng
,
00:55
July 15, 2020
Re: [PATCH for-5.1 1/2] msf2: Unbreak device-list-properties for "msf-soc"
,
sundeep subbaraya
,
23:56
Re: [PATCH for-5.1 2/2] hw: Mark nd_table[] misuse in realize methods FIXME
,
Niek Linnenbank
,
13:09
Re: [PATCH for-5.1 2/2] hw: Mark nd_table[] misuse in realize methods FIXME
,
Alistair Francis
,
10:50
Re: [PATCH for-5.1 1/2] msf2: Unbreak device-list-properties for "msf-soc"
,
Alistair Francis
,
10:49
Re: [PATCH for-5.1 2/2] hw: Mark nd_table[] misuse in realize methods FIXME
,
Markus Armbruster
,
10:45
Re: [PATCH for-5.1 1/2] msf2: Unbreak device-list-properties for "msf-soc"
,
Markus Armbruster
,
10:42
Re: [PATCH for-5.1 0/2] Unbreak make check SPEED=slow
,
no-reply
,
10:31
Re: [PATCH for-5.1 2/2] hw: Mark nd_table[] misuse in realize methods FIXME
,
Thomas Huth
,
10:28
Re: [PATCH for-5.1 1/2] msf2: Unbreak device-list-properties for "msf-soc"
,
Thomas Huth
,
10:25
Re: [PATCH for-5.1 1/2] msf2: Unbreak device-list-properties for "msf-soc"
,
Philippe Mathieu-Daudé
,
10:16
[PATCH for-5.1 1/2] msf2: Unbreak device-list-properties for "msf-soc"
,
Markus Armbruster
,
10:04
[PATCH for-5.1 0/2] Unbreak make check SPEED=slow
,
Markus Armbruster
,
10:04
[PATCH for-5.1 2/2] hw: Mark nd_table[] misuse in realize methods FIXME
,
Markus Armbruster
,
10:04
July 14, 2020
Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
,
LIU Zhiwei
,
22:53
Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
,
Frank Chang
,
09:59
Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
,
Richard Henderson
,
09:22
Re: [RFC 63/65] fpu: implement full set compare for fp16
,
Chih-Min Chao
,
05:29
Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
,
Frank Chang
,
00:39
July 13, 2020
Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
,
LIU Zhiwei
,
23:35
Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
,
Frank Chang
,
22:59
Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
,
Alistair Francis
,
20:53
Re: [PATCH v1] target/riscv: fix pmp implementation
,
Alistair Francis
,
15:44
Re: [RFC 62/65] fpu: add api to handle alternative sNaN propagation
,
Chih-Min Chao
,
13:38
Re: [RFC 00/65] target/riscv: support vector extension v0.9
,
Frank Chang
,
12:44
Re: [RFC 00/65] target/riscv: support vector extension v0.9
,
Richard Henderson
,
12:41
Re: [RFC 00/65] target/riscv: support vector extension v0.9
,
Alistair Francis
,
12:07
Re: [PATCH v1] target/riscv: fix pmp implementation
,
Alexandre Mergnat
,
06:10
July 12, 2020
Re: [RFC 12/65] target/riscv: rvv-0.9: update check functions
,
Frank Chang
,
22:11
Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions
,
Frank Chang
,
22:07
Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions
,
Frank Chang
,
22:05
Re: [RFC 00/65] target/riscv: support vector extension v0.9
,
Frank Chang
,
22:02
Re: [PATCH v4 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Bin Meng
,
21:54
Re: [PATCH v4 7/7] Makefile: Ship the generic platform bios images for RISC-V
,
Bin Meng
,
21:26
Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
,
Bin Meng
,
21:16
Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
,
Bin Meng
,
21:14
July 11, 2020
Re: [PATCH v4 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Alistair Francis
,
13:34
Re: [PATCH v4 7/7] Makefile: Ship the generic platform bios images for RISC-V
,
Alistair Francis
,
13:28
[PATCH 01/11] riscv: Add RV64I instructions description
,
LIU Zhiwei
,
12:19
[PATCH 09/11] riscv: Define riscv struct reginfo
,
LIU Zhiwei
,
12:19
[PATCH 07/11] riscv: Generate payload scripts
,
LIU Zhiwei
,
12:19
[PATCH 03/11] riscv: Add RV64A instructions description
,
LIU Zhiwei
,
12:19
[PATCH 00/11] RISC-V risu porting
,
LIU Zhiwei
,
12:19
[PATCH 11/11] riscv: Add configure script
,
LIU Zhiwei
,
12:19
[PATCH 10/11] riscv: Implement payload load interfaces
,
LIU Zhiwei
,
12:19
[PATCH 08/11] riscv: Add standard test case
,
LIU Zhiwei
,
12:19
[PATCH 06/11] riscv: Add RV64C instructions description
,
LIU Zhiwei
,
12:19
[PATCH 05/11] riscv: Add RV64D instructions description
,
LIU Zhiwei
,
12:19
[PATCH 04/11] riscv: Add RV64F instructions description
,
LIU Zhiwei
,
12:19
[PATCH 02/11] riscv: Add RV64M instructions description
,
LIU Zhiwei
,
12:18
Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
,
Alistair Francis
,
12:04
Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
,
Alistair Francis
,
12:03
July 10, 2020
Re: [RFC 00/65] target/riscv: support vector extension v0.9
,
Alistair Francis
,
17:53
Re: [PATCH v1] target/riscv: fix pmp implementation
,
Alistair Francis
,
16:35
Re: [PATCH v4 0/7] riscv: Switch to use generic platform fw_dynamic type opensbi bios images
,
Alistair Francis
,
15:12
Re: [PATCH v4 0/7] riscv: Switch to use generic platform fw_dynamic type opensbi bios images
,
Alistair Francis
,
15:09
Re: [PATCH v4 7/7] Makefile: Ship the generic platform bios images for RISC-V
,
Alistair Francis
,
14:46
Re: [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
,
Alistair Francis
,
14:34
Re: [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions
,
Alex Bennée
,
14:19
Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions
,
Richard Henderson
,
14:15
Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions
,
Richard Henderson
,
14:07
Re: [RFC 12/65] target/riscv: rvv-0.9: update check functions
,
Richard Henderson
,
13:51
Re: [RFC 11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
,
Richard Henderson
,
13:45
Re: [RFC 10/65] target/riscv: rvv-0.9: remove MLEN calculations
,
Richard Henderson
,
13:32
Re: [RFC 09/65] target/riscv: rvv-0.9: add vlenb register
,
Richard Henderson
,
13:31
Re: [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags
,
Richard Henderson
,
13:28
Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status
,
Richard Henderson
,
13:27
Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status
,
Richard Henderson
,
13:26
Re: [RFC 06/65] target/riscv: rvv-0.9: add vcsr register
,
Richard Henderson
,
13:02
Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
,
Richard Henderson
,
12:27
Re: [RFC 04/65] target/riscv: fix vill bit index in vtype register
,
Richard Henderson
,
12:16
Re: [RFC 03/65] target/riscv: fix return value of do_opivx_widen()
,
Richard Henderson
,
12:15
Re: [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
,
Richard Henderson
,
12:13
Re: [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
,
Richard Henderson
,
12:12
Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
,
Alex Bennée
,
10:59
Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
,
Frank Chang
,
09:13
[RFC 10/65] target/riscv: rvv-0.9: remove MLEN calculations
,
frank . chang
,
08:59
[RFC 64/65] target/riscv: use softfloat lib float16 comparison functions
,
frank . chang
,
08:59
[RFC 62/65] fpu: add api to handle alternative sNaN propagation
,
frank . chang
,
08:59
[RFC 61/65] fpu: fix float16 nan check
,
frank . chang
,
08:59
[RFC 58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert
,
frank . chang
,
08:59
[RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions
,
frank . chang
,
08:59
[RFC 56/65] target/riscv: rvv-0.9: remove integer extract instruction
,
frank . chang
,
08:59
[RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions
,
frank . chang
,
08:59
[RFC 47/65] target/riscv: rvv-0.9: floating-point slide instructions
,
frank . chang
,
08:59
[RFC 45/65] target/riscv: rvv-0.9: register gather instructions
,
frank . chang
,
08:59
[RFC 34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
,
frank . chang
,
08:59
[RFC 30/65] target/riscv: rvv-0.9: floating-point scalar move instructions
,
frank . chang
,
08:59
[RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions
,
frank . chang
,
08:59
[RFC 24/65] target/riscv: rvv-0.9: mask population count instruction
,
frank . chang
,
08:59
[RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions
,
frank . chang
,
08:59
[RFC 16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns
,
frank . chang
,
08:59
[RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags
,
frank . chang
,
08:59
[RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
,
frank . chang
,
08:59
[RFC 65/65] target/riscv: bump to RVV 0.9
,
frank . chang
,
08:59
[RFC 59/65] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
,
frank . chang
,
08:59
[RFC 53/65] target/riscv: rvv-0.9: single-width scaling shift instructions
,
frank . chang
,
08:59
[RFC 51/65] target/riscv: rvv-0.9: single-width floating-point reduction
,
frank . chang
,
08:59
[RFC 49/65] target/riscv: rvv-0.9: floating-point move instructions
,
frank . chang
,
08:59
[RFC 48/65] target/riscv: rvv-0.9: narrowing fixed-point clip instructions
,
frank . chang
,
08:59
[RFC 46/65] target/riscv: rvv-0.9: slide instructions
,
frank . chang
,
08:59
[RFC 42/65] target/riscv: rvv-0.9: single-width integer reduction instructions
,
frank . chang
,
08:59
[RFC 41/65] target/riscv: rvv-0.9: floating-point compare instructions
,
frank . chang
,
08:59
[RFC 36/65] target/riscv: rvv-0.9: widening integer multiply-add instructions
,
frank . chang
,
08:59
[RFC 29/65] target/riscv: rvv-0.9: integer scalar move instructions
,
frank . chang
,
08:59
[RFC 18/65] target/riscv: rvv-0.9: amo operations
,
frank . chang
,
08:59
[RFC 17/65] target/riscv: rvv-0.9: fault-only-first unit stride load
,
frank . chang
,
08:59
[RFC 12/65] target/riscv: rvv-0.9: update check functions
,
frank . chang
,
08:59
[RFC 11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
,
frank . chang
,
08:59
Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
,
Frank Chang
,
08:59
[RFC 63/65] fpu: implement full set compare for fp16
,
frank . chang
,
08:59
[RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
,
frank . chang
,
08:59
[RFC 55/65] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
,
frank . chang
,
08:59
[RFC 54/65] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
,
frank . chang
,
08:59
[RFC 50/65] target/riscv: rvv-0.9: floating-point/integer type-convert instructions
,
frank . chang
,
08:59
[RFC 43/65] target/riscv: rvv-0.9: widening integer reduction instructions
,
frank . chang
,
08:59
[RFC 40/65] target/riscv: rvv-0.9: integer comparison instructions
,
frank . chang
,
08:59
[RFC 39/65] target/riscv: rvv-0.9: single-width saturating add and subtract instructions
,
frank . chang
,
08:59
[RFC 38/65] target/riscv: rvv-0.9: integer merge and move instructions
,
frank . chang
,
08:59
[RFC 35/65] target/riscv: rvv-0.9: narrowing integer right shift instructions
,
frank . chang
,
08:59
[RFC 33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions
,
frank . chang
,
08:59
[RFC 32/65] target/riscv: rvv-0.9: integer extension instructions
,
frank . chang
,
08:59
[RFC 28/65] target/riscv: rvv-0.9: element index instruction
,
frank . chang
,
08:59
[RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction
,
frank . chang
,
08:59
[RFC 21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation
,
frank . chang
,
08:59
[RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
,
frank . chang
,
08:59
[RFC 15/65] target/riscv: rvv-0.9: index load and store instructions
,
frank . chang
,
08:59
[RFC 13/65] target/riscv: rvv-0.9: configure instructions
,
frank . chang
,
08:59
[RFC 09/65] target/riscv: rvv-0.9: add vlenb register
,
frank . chang
,
08:59
[RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
,
frank . chang
,
08:59
[RFC 04/65] target/riscv: fix vill bit index in vtype register
,
frank . chang
,
08:59
[RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
,
frank . chang
,
08:59
[RFC 00/65] target/riscv: support vector extension v0.9
,
frank . chang
,
08:59
[RFC 31/65] target/riscv: rvv-0.9: whole register move instructions
,
frank . chang
,
08:59
[RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction
,
frank . chang
,
08:59
[RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions
,
frank . chang
,
08:59
[RFC 07/65] target/riscv: rvv-0.9: add vector context status
,
frank . chang
,
08:59
[RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions
,
frank . chang
,
08:59
[RFC 06/65] target/riscv: rvv-0.9: add vcsr register
,
frank . chang
,
08:59
[RFC 03/65] target/riscv: fix return value of do_opivx_widen()
,
frank . chang
,
08:59
[RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions
,
frank . chang
,
08:59
[RFC 37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
,
frank . chang
,
08:59
[RFC 27/65] target/riscv: rvv-0.9: iota instruction
,
frank . chang
,
08:59
Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
,
Alex Bennée
,
08:46
Re: [RFC 63/65] fpu: implement full set compare for fp16
,
Alex Bennée
,
08:27
Re: [RFC 63/65] fpu: implement full set compare for fp16
,
Alex Bennée
,
08:24
Re: [RFC 62/65] fpu: add api to handle alternative sNaN propagation
,
Alex Bennée
,
08:15
Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
,
Alex Bennée
,
08:07
[PATCH v4 7/7] Makefile: Ship the generic platform bios images for RISC-V
,
Bin Meng
,
01:05
[PATCH v4 6/7] gitlab-ci/opensbi: Update GitLab CI to build generic platform
,
Bin Meng
,
01:05
[PATCH v4 5/7] hw/riscv: spike: Change the default bios to use generic platform image
,
Bin Meng
,
01:05
[PATCH v4 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Bin Meng
,
01:05
[PATCH v4 3/7] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware
,
Bin Meng
,
01:05
[PATCH v4 2/7] roms/opensbi: Upgrade from v0.7 to v0.8
,
Bin Meng
,
01:05
[PATCH v4 1/7] configure: Create symbolic links for pc-bios/*.elf files
,
Bin Meng
,
01:05
[PATCH v4 0/7] riscv: Switch to use generic platform fw_dynamic type opensbi bios images
,
Bin Meng
,
01:05
July 09, 2020
Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
,
Bin Meng
,
20:50
Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
,
Bin Meng
,
20:48
Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
,
Palmer Dabbelt
,
20:45
Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
,
Alistair Francis
,
18:19
[PATCH v2 v2 2/2] hw/char: Convert the Ibex UART to use the registerfields API
,
Alistair Francis
,
18:14
[PATCH v2 v2 1/2] hw/char: Convert the Ibex UART to use the qdev Clock model
,
Alistair Francis
,
18:14
[PATCH v2 v2 0/2] A few RISC-V fixes
,
Alistair Francis
,
18:14
Re: [PATCH v2 1/2] hw/riscv: Modify MROM size to end at 0x10000
,
Alistair Francis
,
13:28
[PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
,
Bin Meng
,
06:05
[PATCH v2 1/2] hw/riscv: Modify MROM size to end at 0x10000
,
Bin Meng
,
06:05
Re: [PATCH 1/2] hw/riscv: Modify MROM size to end at 0x10000
,
Bin Meng
,
06:04
Re: [PATCH 1/2] hw/riscv: Modify MROM size to end at 0x10000
,
Philippe Mathieu-Daudé
,
01:15
July 08, 2020
[PATCH 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
,
Bin Meng
,
21:09
[PATCH 1/2] hw/riscv: Modify MROM size to end at 0x10000
,
Bin Meng
,
21:09
July 07, 2020
Re: [PATCH v1 3/3] target/riscv: Regen floating point rounding mode in dynamic mode
,
Bin Meng
,
20:36
Re: [PATCH v3 7/7] Makefile: Ship the generic platform bios images for RISC-V
,
Alistair Francis
,
19:27
Re: [PATCH v3 6/7] gitlab-ci/opensbi: Update GitLab CI to build generic platform
,
Alistair Francis
,
19:25
Re: [PATCH v3 3/7] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware
,
Alistair Francis
,
18:40
Re: [PATCH] load_elf: Remove unused address variables from callers
,
Max Filippov
,
15:17
Re: [PATCH] load_elf: Remove unused address variables from callers
,
BALATON Zoltan
,
14:55
Re: [PATCH v4 0/4] Add OpenSBI dynamic firmware support
,
Alistair Francis
,
13:53
Re: [PATCH v4 4/4] RISC-V: Support 64 bit start address
,
Alistair Francis
,
13:40
Re: [PATCH v1 3/3] target/riscv: Regen floating point rounding mode in dynamic mode
,
Alistair Francis
,
13:33
Re: [PATCH v1 1/3] hw/char: Convert the Ibex UART to use the qdev Clock model
,
Alistair Francis
,
13:30
Re: [PATCH] load_elf: Remove unused address variables from callers
,
Alistair Francis
,
12:10
Re: [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand.
,
吴伟
,
11:48
Re: [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand.
,
Alistair Francis
,
11:15
[PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand.
,
吴伟
,
10:37
[PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand.
,
lazyparser
,
10:37
Re: [PATCH] riscv: Add OpenTitan Big Number (OTBN) device address
,
Bin Meng
,
05:08
[PATCH] riscv: Add OpenTitan Big Number (OTBN) device address
,
Julio Faracco
,
01:05
July 06, 2020
Re: [PATCH] hw/riscv: virt: Sort the SoC memmap table entries
,
Alistair Francis
,
14:49
Re: [PATCH] hw/riscv: virt: Sort the SoC memmap table entries
,
Alistair Francis
,
14:45
Re: [RFC PATCH v2 21/23] hw/riscv: Emit warning when old code is used
,
Alistair Francis
,
12:56
Re: [RFC PATCH v2 08/23] hw/display/ramfb: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
10:18
Re: [RFC PATCH v2 08/23] hw/display/ramfb: Emit warning when old code is used
,
Gerd Hoffmann
,
10:15
[PATCH v1] target/riscv: fix pmp implementation
,
Alexandre Mergnat
,
05:43
July 05, 2020
Re: [PATCH] load_elf: Remove unused address variables from callers
,
David Gibson
,
23:58
[PATCH] load_elf: Remove unused address variables from callers
,
BALATON Zoltan
,
13:40
Re: [RFC PATCH v2 15/23] hw/m68k/mcf520x: Emit warning when old code is used
,
Thomas Huth
,
02:31
July 04, 2020
Re: [RFC PATCH v2 02/23] hw/core/qdev: Add qdev_warn_deprecated_function_used() helper
,
BALATON Zoltan
,
12:22
Re: [RFC PATCH v2 18/23] hw/openrisc/cputimer: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:47
[RFC PATCH v2 23/23] hw/xtensa/xtfpga: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:41
[RFC PATCH v2 22/23] hw/usb/hcd-musb: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:41
[RFC PATCH v2 21/23] hw/riscv: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:41
[RFC PATCH v2 20/23] hw/sh4: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:41
[RFC PATCH v2 19/23] hw/ppc/ppc4xx: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:41
[RFC PATCH v2 18/23] hw/openrisc/cputimer: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:41
[RFC PATCH v2 17/23] hw/nvram/eeprom93xx: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:40
[RFC PATCH v2 16/23] hw/misc/cbus: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:40
[RFC PATCH v2 15/23] hw/m68k/mcf520x: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:40
[RFC PATCH v2 14/23] hw/input/tsc2005: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:40
[RFC PATCH v2 12/23] hw/dma/soc_dma: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:40
[RFC PATCH v2 13/23] hw/input/lasips2: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:40
[RFC PATCH v2 11/23] hw/dma/etraxfs_dma: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:40
[RFC PATCH v2 10/23] hw/display/vga-isa-mm: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:40
[RFC PATCH v2 09/23] hw/display/tc6393xb: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:40
[RFC PATCH v2 08/23] hw/display/ramfb: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:40
[RFC PATCH v2 07/23] hw/display/blizzard: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:39
[RFC PATCH v2 06/23] hw/char/parallel: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:39
[RFC PATCH v2 05/23] hw/arm/nseries: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:39
[RFC PATCH v2 04/23] hw/arm/pxa2xx: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:39
[RFC PATCH v2 03/23] hw/arm/omap: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
11:39
[RFC PATCH v2 02/23] hw/core/qdev: Add qdev_warn_deprecated_function_used() helper
,
Philippe Mathieu-Daudé
,
11:39
[PATCH v2 01/23] qom/object: Update documentation
,
Philippe Mathieu-Daudé
,
11:39
[RFC PATCH v2 00/23] hw/qdev: Warn when using pre-qdev/QOM devices
,
Philippe Mathieu-Daudé
,
11:39
July 03, 2020
Re: [PATCH v1 2/3] hw/riscv: Allow 64 bit access to SiFive CLINT
,
Philippe Mathieu-Daudé
,
03:44
Re: [PATCH v1 1/3] hw/char: Convert the Ibex UART to use the qdev Clock model
,
Philippe Mathieu-Daudé
,
03:42
July 02, 2020
[PATCH] hw/riscv: virt: Sort the SoC memmap table entries
,
Bin Meng
,
23:22
[PATCH v3 7/7] Makefile: Ship the generic platform bios images for RISC-V
,
Bin Meng
,
23:18
[PATCH v3 6/7] gitlab-ci/opensbi: Update GitLab CI to build generic platform
,
Bin Meng
,
23:18
[PATCH v3 5/7] hw/riscv: spike: Change the default bios to use generic platform image
,
Bin Meng
,
23:18
[PATCH v3 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Bin Meng
,
23:18
[PATCH v3 3/7] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware
,
Bin Meng
,
23:18
[PATCH v3 2/7] roms/opensbi: Upgrade from v0.7 to v0.8
,
Bin Meng
,
23:18
[PATCH v3 1/7] configure: Create symbolic links for pc-bios/*.elf files
,
Bin Meng
,
23:18
[PATCH v3 0/7] riscv: Switch to use generic platform fw_dynamic type opensbi bios images
,
Bin Meng
,
23:18
Re: [PATCH v1 3/3] target/riscv: Regen floating point rounding mode in dynamic mode
,
Bin Meng
,
21:25
Re: [PATCH v4 4/4] RISC-V: Support 64 bit start address
,
Bin Meng
,
21:19
Re: [PATCH v4 3/4] riscv: Add opensbi firmware dynamic support
,
Bin Meng
,
21:19
Re: [PATCH v4 2/4] RISC-V: Copy the fdt in dram instead of ROM
,
Bin Meng
,
21:19
Re: [PATCH 6/6] target/riscv: clean up fmv.w.x
,
Richard Henderson
,
13:38
Re: [PATCH 0/6] target/riscv: NaN-boxing for multiple precison
,
Richard Henderson
,
13:37
Re: [PATCH 2/6] target/riscv: NaN-boxing compute, sign-injection and convert instructions.
,
Richard Henderson
,
13:15
Re: [PATCH 4/6] target/riscv: check before allocating TCG temps
,
Richard Henderson
,
13:13
Re: [PATCH 1/6] target/riscv: move gen_nanbox_fpr to translate.c
,
Richard Henderson
,
13:13
[PULL 19/28] riscv/sifive_u: Fix sifive_u_soc_realize() error API violations
,
Markus Armbruster
,
07:10
[PULL 20/28] riscv_hart: Fix riscv_harts_realize() error API violations
,
Markus Armbruster
,
07:09
Re: [PATCH 5/6] target/riscv: Flush not valid NaN-boxing input to canonical NaN
,
Chih-Min Chao
,
02:29
July 01, 2020
Re: [PATCH v1 2/3] hw/riscv: Allow 64 bit access to SiFive CLINT
,
Alistair Francis
,
23:43
Re: [PATCH v12 00/61] target/riscv: support vector extension v0.7.1
,
Alistair Francis
,
23:41
Re: [PATCH 1/1] tcg/tcg-op: nonatomic_op should work with smaller memop
,
LIU Zhiwei
,
19:44
Re: [PATCH v12 00/61] target/riscv: support vector extension v0.7.1
,
no-reply
,
15:38
[PATCH v4 4/4] RISC-V: Support 64 bit start address
,
Atish Patra
,
14:40
[PATCH v4 2/4] RISC-V: Copy the fdt in dram instead of ROM
,
Atish Patra
,
14:40
[PATCH v4 3/4] riscv: Add opensbi firmware dynamic support
,
Atish Patra
,
14:40
[PATCH v4 0/4] Add OpenSBI dynamic firmware support
,
Atish Patra
,
14:40
[PATCH v4 1/4] riscv: Unify Qemu's reset vector code path
,
Atish Patra
,
14:40
[PATCH v12 61/61] target/riscv: configure and turn on vector extension from command line
,
LIU Zhiwei
,
13:29
[PATCH v12 60/61] target/riscv: vector compress instruction
,
LIU Zhiwei
,
13:27
[PATCH v12 59/61] target/riscv: vector register gather instruction
,
LIU Zhiwei
,
13:25
[PATCH v12 58/61] target/riscv: vector slide instructions
,
LIU Zhiwei
,
13:23
[PATCH v12 57/61] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
13:21
[PATCH v12 56/61] target/riscv: integer scalar move instruction
,
LIU Zhiwei
,
13:19
[PATCH v12 55/61] target/riscv: integer extract instruction
,
LIU Zhiwei
,
13:17
[PATCH v12 54/61] target/riscv: vector element index instruction
,
LIU Zhiwei
,
13:15
[PATCH v12 53/61] target/riscv: vector iota instruction
,
LIU Zhiwei
,
13:13
[PATCH v12 52/61] target/riscv: set-X-first mask bit
,
LIU Zhiwei
,
13:11
[PATCH v12 51/61] target/riscv: vmfirst find-first-set mask bit
,
LIU Zhiwei
,
13:08
[PATCH v12 50/61] target/riscv: vector mask population count vmpopc
,
LIU Zhiwei
,
13:07
[PATCH v12 49/61] target/riscv: vector mask-register logical instructions
,
LIU Zhiwei
,
13:05
[PATCH v12 48/61] target/riscv: vector widening floating-point reduction instructions
,
LIU Zhiwei
,
13:03
[PATCH v12 47/61] target/riscv: vector single-width floating-point reduction instructions
,
LIU Zhiwei
,
13:01
[PATCH v12 46/61] target/riscv: vector wideing integer reduction instructions
,
LIU Zhiwei
,
12:58
[PATCH v12 45/61] target/riscv: vector single-width integer reduction instructions
,
LIU Zhiwei
,
12:56
[PATCH v12 44/61] target/riscv: narrowing floating-point/integer type-convert instructions
,
LIU Zhiwei
,
12:54
[PATCH v12 43/61] target/riscv: widening floating-point/integer type-convert instructions
,
LIU Zhiwei
,
12:52
[PATCH v12 42/61] target/riscv: vector floating-point/integer type-convert instructions
,
LIU Zhiwei
,
12:50
[PATCH v12 41/61] target/riscv: vector floating-point merge instructions
,
LIU Zhiwei
,
12:48
[PATCH v12 40/61] target/riscv: vector floating-point classify instructions
,
LIU Zhiwei
,
12:46
[PATCH v12 39/61] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
12:44
[PATCH v12 38/61] target/riscv: vector floating-point sign-injection instructions
,
LIU Zhiwei
,
12:42
[PATCH v12 37/61] target/riscv: vector floating-point min/max instructions
,
LIU Zhiwei
,
12:40
[PATCH v12 36/61] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
12:38
[PATCH v12 35/61] target/riscv: vector widening floating-point fused multiply-add instructions
,
LIU Zhiwei
,
12:36
[PATCH v12 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
12:34
[PATCH v12 33/61] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
12:32
[PATCH v12 32/61] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
12:30
[PATCH v12 31/61] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
12:28
[PATCH v12 30/61] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
12:26
Re: [PATCH 1/1] tcg/tcg-op: nonatomic_op should work with smaller memop
,
Richard Henderson
,
12:26
[PATCH v12 29/61] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
12:24
[PATCH v12 28/61] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
12:22
[PATCH v12 27/61] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
12:20
[PATCH v12 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
12:18
[PATCH v12 25/61] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
12:16
[PATCH v12 24/61] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
12:14
[PATCH v12 23/61] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
12:12
[PATCH v12 22/61] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
12:10
[PATCH v12 21/61] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
12:08
[PATCH v12 20/61] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
12:06
[PATCH v12 19/61] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
12:04
[PATCH v12 18/61] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
12:02
[PATCH v12 17/61] target/riscv: vector integer min/max instructions
,
LIU Zhiwei
,
12:00
[PATCH v12 16/61] target/riscv: vector integer comparison instructions
,
LIU Zhiwei
,
11:58
[PATCH v12 15/61] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
11:56
[PATCH v12 14/61] target/riscv: vector single-width bit shift instructions
,
LIU Zhiwei
,
11:54
[PATCH v12 13/61] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
11:52
[PATCH v12 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
11:50
[PATCH v12 11/61] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
11:48
[PATCH v12 10/61] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
11:46
[PATCH v12 09/61] target/riscv: add vector amo operations
,
LIU Zhiwei
,
11:44
[PATCH v12 08/61] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
11:42
[PATCH v12 07/61] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
11:40
[PATCH v12 06/61] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
11:38
[PATCH v12 05/61] target/riscv: add an internals.h header
,
LIU Zhiwei
,
11:36
[PATCH v12 04/61] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
11:34
[PATCH v12 03/61] target/riscv: support vector extension csr
,
LIU Zhiwei
,
11:32
[PATCH v12 02/61] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
11:30
[PATCH v12 01/61] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
11:28
[PATCH v12 00/61] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
11:26
[PATCH 1/1] tcg/tcg-op: nonatomic_op should work with smaller memop
,
LIU Zhiwei
,
11:22
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