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[RFC v2 52/76] fpu: implement full set compare for fp16
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From: |
frank . chang |
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Subject: |
[RFC v2 52/76] fpu: implement full set compare for fp16 |
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Date: |
Wed, 22 Jul 2020 17:16:15 +0800 |
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat.c | 28 ++++++++++++++++++++++++++++
include/fpu/softfloat.h | 41 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 69 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 79be4f5840..9c6640862e 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -401,6 +401,34 @@ float64_gen2(float64 xa, float64 xb, float_status *s,
return soft(ua.s, ub.s, s);
}
+/*----------------------------------------------------------------------------
+| Returns the fraction bits of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline uint32_t extractFloat16Frac(float16 a)
+{
+ return float16_val(a) & 0x3ff;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the exponent bits of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline int extractFloat16Exp(float16 a)
+{
+ return (float16_val(a) >> 10) & 0x1f;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the sign bit of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline bool extractFloat16Sign(float16 a)
+{
+ return float16_val(a) >> 15;
+}
+
+
/*----------------------------------------------------------------------------
| Returns the fraction bits of the single-precision floating-point value `a'.
*----------------------------------------------------------------------------*/
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index ff4e2605b1..267519cd65 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -285,6 +285,47 @@ static inline float16 float16_set_sign(float16 a, int sign)
return make_float16((float16_val(a) & 0x7fff) | (sign << 15));
}
+static inline bool float16_eq(float16 a, float16 b, float_status *s)
+{
+ return float16_compare(a, b, s) == float_relation_equal;
+}
+
+static inline bool float16_le(float16 a, float16 b, float_status *s)
+{
+ return float16_compare(a, b, s) <= float_relation_equal;
+}
+
+static inline bool float16_lt(float16 a, float16 b, float_status *s)
+{
+ return float16_compare(a, b, s) < float_relation_equal;
+}
+
+static inline bool float16_unordered(float16 a, float16 b, float_status *s)
+{
+ return float16_compare(a, b, s) == float_relation_unordered;
+}
+
+static inline bool float16_eq_quiet(float16 a, float16 b, float_status *s)
+{
+ return float16_compare_quiet(a, b, s) == float_relation_equal;
+}
+
+static inline bool float16_le_quiet(float16 a, float16 b, float_status *s)
+{
+ return float16_compare_quiet(a, b, s) <= float_relation_equal;
+}
+
+static inline bool float16_lt_quiet(float16 a, float16 b, float_status *s)
+{
+ return float16_compare_quiet(a, b, s) < float_relation_equal;
+}
+
+static inline bool float16_unordered_quiet(float16 a, float16 b,
+ float_status *s)
+{
+ return float16_compare_quiet(a, b, s) == float_relation_unordered;
+}
+
#define float16_zero make_float16(0)
#define float16_half make_float16(0x3800)
#define float16_one make_float16(0x3c00)
--
2.17.1
- [RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions, (continued)
- [RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions, frank . chang, 2020/07/22
- [RFC v2 48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions, frank . chang, 2020/07/22
- [RFC v2 49/76] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions, frank . chang, 2020/07/22
- [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions, frank . chang, 2020/07/22
- [RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions, frank . chang, 2020/07/22
- [RFC v2 52/76] fpu: implement full set compare for fp16,
frank . chang <=
- [RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions, frank . chang, 2020/07/22
- [RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions, frank . chang, 2020/07/22
- [RFC v2 55/76] target/riscv: rvv-0.9: single-width integer reduction instructions, frank . chang, 2020/07/22
- [RFC v2 56/76] target/riscv: rvv-0.9: widening integer reduction instructions, frank . chang, 2020/07/22
- [RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions, frank . chang, 2020/07/22
- [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions, frank . chang, 2020/07/22