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Re: [RFC v4 23/70] target/riscv: rvv-1.0: load/store whole register inst
From: |
Richard Henderson |
Subject: |
Re: [RFC v4 23/70] target/riscv: rvv-1.0: load/store whole register instructions |
Date: |
Sat, 29 Aug 2020 12:13:26 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/17/20 1:49 AM, frank.chang@sifive.com wrote:
> +/*
> + * load and store whole register instructions ignore vtype and vl setting.
> + * Thus, we don't need to check vill bit. (Section 7.9)
> + */
> +#define GEN_LDST_WHOLE_TRANS(NAME, EEW, ARGTYPE, ARG_NF, IS_STORE) \
> +static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \
> +{ \
> + if (require_rvv(s) && \
> + QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \
> + uint32_t data = 0; \
> + bool ret; \
> + data = FIELD_DP32(data, VDATA, NF, ARG_NF); \
> + ret = ldst_whole_trans(a->rd, a->rs1, data, gen_helper_##NAME, \
> + s, IS_STORE); \
> + return ret; \
> + } \
> + return false; \
> +}
Decodetree is intentionally organized such that ARGTYPE = NAME. There's no
point in duplicating that. Move everything besides the call to
ldst_whole_trans into ldst_whole_trans.
r~
- Re: [RFC v4 18/70] target/riscv: rvv-1.0: stride load and store instructions, (continued)
- [RFC v4 19/70] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2020/08/17
- [RFC v4 20/70] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/08/17
- [RFC v4 21/70] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2020/08/17
- [RFC v4 22/70] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/08/17
- [RFC v4 23/70] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/08/17
- Re: [RFC v4 23/70] target/riscv: rvv-1.0: load/store whole register instructions,
Richard Henderson <=
- [RFC v4 24/70] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/08/17
- [RFC v4 25/70] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/08/17
- [RFC v4 26/70] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/08/17
- [RFC v4 27/70] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/08/17
- [RFC v4 28/70] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/08/17
- [RFC v4 29/70] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/08/17
- [RFC v4 30/70] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/08/17
- [RFC v4 31/70] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/08/17