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[PATCH v4 00/16] RISC-V: Start to remove xlen preprocess
From: |
Alistair Francis |
Subject: |
[PATCH v4 00/16] RISC-V: Start to remove xlen preprocess |
Date: |
Wed, 16 Dec 2020 10:22:23 -0800 |
The RISC-V QEMU port currently has lot of preprocessor directives that
check if we are targetting a 32-bit or 64-bit CPU. This means that the
64-bit RISC-V target can not run 32-bit CPUs. This is different to most
other QEMU architectures and doesn't allow us to mix xlens (such as when
running Hypervisors with different xlen guests).
This series is a step toward removing some of those to allow us to use
32-bit CPUs on 64-bit RISC-V targets.
v4:
- Add a commit that converts the machine 32-bit check to use the CPU
v3:
- Address Richard's comments
v2:
- Rebase on the latest RISC-V tree
Alistair Francis (16):
hw/riscv: Expand the is 32-bit check to support more CPUs
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
riscv: spike: Remove target macro conditionals
riscv: virt: Remove target macro conditionals
hw/riscv: boot: Remove compile time XLEN checks
hw/riscv: virt: Remove compile time XLEN checks
hw/riscv: spike: Remove compile time XLEN checks
hw/riscv: sifive_u: Remove compile time XLEN checks
target/riscv: fpu_helper: Match function defs in HELPER macros
target/riscv: Add a riscv_cpu_is_32bit() helper function
target/riscv: Specify the XLEN for CPUs
target/riscv: cpu: Remove compile time XLEN checks
target/riscv: cpu_helper: Remove compile time XLEN checks
target/riscv: csr: Remove compile time XLEN checks
target/riscv: cpu: Set XLEN independently from target
hw/riscv: Use the CPU to determine if 32-bit
include/hw/riscv/boot.h | 14 +--
include/hw/riscv/spike.h | 6 --
include/hw/riscv/virt.h | 6 --
target/riscv/cpu.h | 8 ++
target/riscv/cpu_bits.h | 4 +-
target/riscv/helper.h | 24 ++----
hw/riscv/boot.c | 70 ++++++++-------
hw/riscv/sifive_u.c | 59 +++++++------
hw/riscv/spike.c | 52 +++++------
hw/riscv/virt.c | 39 +++++----
target/riscv/cpu.c | 84 ++++++++++++------
target/riscv/cpu_helper.c | 12 +--
target/riscv/csr.c | 176 ++++++++++++++++++++------------------
target/riscv/fpu_helper.c | 8 --
14 files changed, 299 insertions(+), 263 deletions(-)
--
2.29.2
- [PATCH v4 00/16] RISC-V: Start to remove xlen preprocess,
Alistair Francis <=
- [PATCH v4 02/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/12/16
- [PATCH v4 03/16] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/12/16
- [PATCH v4 01/16] hw/riscv: Expand the is 32-bit check to support more CPUs, Alistair Francis, 2020/12/16
- [PATCH v4 04/16] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/16
- [PATCH v4 05/16] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 06/16] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 07/16] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 08/16] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 09/16] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/16