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[PATCH v6 02/72] target/riscv: Use FIELD_EX32() to extract wd field
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From: |
frank . chang |
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Subject: |
[PATCH v6 02/72] target/riscv: Use FIELD_EX32() to extract wd field |
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Date: |
Tue, 12 Jan 2021 17:38:36 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a156573d281..bc3f212ceac 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -98,7 +98,7 @@ static inline uint32_t vext_lmul(uint32_t desc)
static uint32_t vext_wd(uint32_t desc)
{
- return (simd_data(desc) >> 11) & 0x1;
+ return FIELD_EX32(simd_data(desc), VDATA, WD);
}
/*
--
2.17.1
- [PATCH v6 00/72] support vector extension v1.0, frank . chang, 2021/01/12
- [PATCH v6 01/72] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/01/12
- [PATCH v6 02/72] target/riscv: Use FIELD_EX32() to extract wd field,
frank . chang <=
- [PATCH v6 03/72] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/01/12
- [PATCH v6 04/72] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/01/12
- [PATCH v6 06/72] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/01/12
- [PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/01/12
- [PATCH v6 08/72] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/01/12