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qemu-riscv (date)
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Last Modified: Sun Jan 31 2021 10:34:19 -0500
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January 31, 2021
Re: [PATCH 05/10] meson: Introduce target-specific Kconfig
,
Philippe Mathieu-Daudé
,
10:34
Re: [PATCH 05/10] meson: Introduce target-specific Kconfig
,
Artyom Tarasenko
,
10:17
Re: [PATCH 05/10] meson: Introduce target-specific Kconfig
,
Philippe Mathieu-Daudé
,
07:36
[PATCH 10/10] target: Move SEMIHOSTING feature to target Kconfig
,
Philippe Mathieu-Daudé
,
06:14
[PATCH 09/10] target: Move ARM_COMPATIBLE_SEMIHOSTING feature to target Kconfig
,
Philippe Mathieu-Daudé
,
06:14
[PATCH 08/10] default-configs: Remove unnecessary SEMIHOSTING selection
,
Philippe Mathieu-Daudé
,
06:14
[PATCH 07/10] target/arm: Move V7M feature to target Kconfig
,
Philippe Mathieu-Daudé
,
06:14
[PATCH 06/10] target/i386: Move SEV feature to target Kconfig
,
Philippe Mathieu-Daudé
,
06:14
[PATCH 05/10] meson: Introduce target-specific Kconfig
,
Philippe Mathieu-Daudé
,
06:14
[PATCH 04/10] hw/lm32/Kconfig: Have MILKYMIST select LM32_PERIPHERALS
,
Philippe Mathieu-Daudé
,
06:13
[PATCH 03/10] hw/sh4/Kconfig: Rename CONFIG_LM32 -> CONFIG_LM32_PERIPHERALS
,
Philippe Mathieu-Daudé
,
06:13
[PATCH 02/10] hw/lm32/Kconfig: Introduce CONFIG_LM32_EVR for lm32-evr/uclinux boards
,
Philippe Mathieu-Daudé
,
06:13
[PATCH 01/10] hw/sh4/Kconfig: Rename CONFIG_SH4 -> CONFIG_SH4_PERIPHERALS
,
Philippe Mathieu-Daudé
,
06:13
[PATCH 00/10] target: Provide target-specific Kconfig
,
Philippe Mathieu-Daudé
,
06:13
January 28, 2021
Re: [PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs
,
Alistair Francis
,
16:27
Re: [PATCH v6 36/72] target/riscv: rvv-1.0: floating-point move instruction
,
Alistair Francis
,
16:21
Re: [PATCH v6 34/72] target/riscv: rvv-1.0: register gather instructions
,
Alistair Francis
,
16:19
Re: [PATCH v6 14/72] target/riscv: rvv-1.0: update check functions
,
Alistair Francis
,
16:15
Re: [PATCH v3 1/9] hw/block: m25p80: Add ISSI SPI flash support
,
Alistair Francis
,
15:57
January 27, 2021
Re: [PATCH v3 9/9] docs/system: riscv: Add documentation for sifive_u machine
,
Palmer Dabbelt
,
00:51
January 26, 2021
Re: [PATCH v2 06/25] util: Add CRC16 (CCITT) calculation routines
,
Philippe Mathieu-Daudé
,
02:45
Re: [PATCH v6 68/72] target/riscv: gdb: modify gdb csr xml file to align with csr register map
,
Frank Chang
,
02:44
Re: [PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support
,
Philippe Mathieu-Daudé
,
02:34
Re: [PATCH v6 00/72] support vector extension v1.0
,
Frank Chang
,
01:14
[PATCH v3 9/9] docs/system: riscv: Add documentation for sifive_u machine
,
Bin Meng
,
01:01
[PATCH v3 8/9] docs/system: Add RISC-V documentation
,
Bin Meng
,
01:01
[PATCH v3 7/9] docs/system: Sort targets in alphabetical order
,
Bin Meng
,
01:01
[PATCH v3 6/9] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
,
Bin Meng
,
01:00
[PATCH v3 5/9] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
,
Bin Meng
,
01:00
[PATCH v3 4/9] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
,
Bin Meng
,
01:00
[PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support
,
Bin Meng
,
01:00
[PATCH v3 2/9] hw/block: m25p80: Add various ISSI flash information
,
Bin Meng
,
01:00
[PATCH v3 1/9] hw/block: m25p80: Add ISSI SPI flash support
,
Bin Meng
,
01:00
[PATCH v3 0/9] hw/riscv: sifive_u: Add missing SPI support
,
Bin Meng
,
01:00
January 25, 2021
Re: [PATCH v6 68/72] target/riscv: gdb: modify gdb csr xml file to align with csr register map
,
Alistair Francis
,
18:54
Re: [PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions
,
Alistair Francis
,
18:50
Re: [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction
,
Alistair Francis
,
18:49
Re: [RFC v4 01/16] target/riscv: reformat @sh format encoding for B-extension
,
Alistair Francis
,
18:47
Re: [PATCH v2 6/7] goldfish_rtc: re-arm the alarm after migration
,
Alistair Francis
,
18:45
Re: [PATCH v6 25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
,
Alistair Francis
,
18:43
Re: [PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
,
Alistair Francis
,
18:33
Re: [PATCH v6 23/72] target/riscv: rvv-1.0: load/store whole register instructions
,
Alistair Francis
,
18:25
Re: [PATCH v6 22/72] target/riscv: rvv-1.0: amo operations
,
Alistair Francis
,
18:20
Re: [PATCH 1/4] hw/riscv: Drop 'struct MemmapEntry'
,
Philippe Mathieu-Daudé
,
12:41
Re: [PATCH v2 18/25] hw/sd: ssi-sd: Bump up version ids of VMStateDescription
,
Bin Meng
,
05:48
Re: [PATCH v2 18/25] hw/sd: ssi-sd: Bump up version ids of VMStateDescription
,
Dr. David Alan Gilbert
,
05:41
January 24, 2021
Re: [PATCH v2 18/25] hw/sd: ssi-sd: Bump up version ids of VMStateDescription
,
Bin Meng
,
20:21
Re: [PATCH v2 09/25] hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION
,
Bin Meng
,
19:42
Re: [PATCH v2 09/25] hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION
,
Bin Meng
,
19:33
Re: [PATCH v2 06/25] util: Add CRC16 (CCITT) calculation routines
,
Richard Henderson
,
16:41
Re: [PATCH v2 06/25] util: Add CRC16 (CCITT) calculation routines
,
Philippe Mathieu-Daudé
,
15:24
Re: [PATCH v2 06/25] util: Add CRC16 (CCITT) calculation routines
,
Richard Henderson
,
15:07
Re: [PATCH v2 00/25] hw/riscv: sifive_u: Add missing SPI support
,
Philippe Mathieu-Daudé
,
15:07
Re: [PATCH v2 06/25] util: Add CRC16 (CCITT) calculation routines
,
Philippe Mathieu-Daudé
,
13:59
Re: [PATCH v2 07/25] hw/sd: ssi-sd: Suffix a data block with CRC16
,
Philippe Mathieu-Daudé
,
13:57
Re: [PATCH v2 05/25] hw/sd: sd: Drop sd_crc16()
,
Philippe Mathieu-Daudé
,
13:14
Re: [PATCH v2 03/25] hw/sd: ssi-sd: Fix incorrect card response sequence
,
Philippe Mathieu-Daudé
,
12:48
Re: [PATCH v2 08/25] hw/sd: ssi-sd: Add a state representing Nac
,
Philippe Mathieu-Daudé
,
12:47
Re: [PATCH v2 14/25] hw/sd: sd.h: Cosmetic change of using spaces
,
Philippe Mathieu-Daudé
,
12:43
Re: [PATCH v2 11/25] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer
,
Philippe Mathieu-Daudé
,
12:37
Re: [PATCH v2 09/25] hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION
,
Philippe Mathieu-Daudé
,
12:35
Re: [PATCH v2 09/25] hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION
,
Philippe Mathieu-Daudé
,
12:33
Re: [PATCH v2 08/25] hw/sd: ssi-sd: Add a state representing Nac
,
Philippe Mathieu-Daudé
,
12:26
Re: [PATCH v2 04/25] hw/sd: sd: Support CMD59 for SPI mode
,
Philippe Mathieu-Daudé
,
12:21
Re: [PATCH v2 18/25] hw/sd: ssi-sd: Bump up version ids of VMStateDescription
,
Philippe Mathieu-Daudé
,
12:07
Re: [PATCH v2 18/25] hw/sd: ssi-sd: Bump up version ids of VMStateDescription
,
Philippe Mathieu-Daudé
,
11:59
January 23, 2021
Re: [PATCH v2 6/7] goldfish_rtc: re-arm the alarm after migration
,
Laurent Vivier
,
10:05
[PATCH v2 24/25] docs/system: Add RISC-V documentation
,
Bin Meng
,
05:42
[PATCH v2 21/25] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
,
Bin Meng
,
05:42
[PATCH v2 22/25] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
,
Bin Meng
,
05:42
[PATCH v2 20/25] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
,
Bin Meng
,
05:42
[PATCH v2 25/25] docs/system: riscv: Add documentation for sifive_u machine
,
Bin Meng
,
05:42
[PATCH v2 23/25] docs/system: Sort targets in alphabetical order
,
Bin Meng
,
05:42
[PATCH v2 19/25] hw/ssi: Add SiFive SPI controller support
,
Bin Meng
,
05:42
[PATCH v2 16/25] hw/sd: ssi-sd: Support single block write
,
Bin Meng
,
05:42
[PATCH v2 15/25] hw/sd: Introduce receive_ready() callback
,
Bin Meng
,
05:42
[PATCH v2 14/25] hw/sd: sd.h: Cosmetic change of using spaces
,
Bin Meng
,
05:42
[PATCH v2 13/25] hw/sd: sd: Allow single/multiple block write for SPI mode
,
Bin Meng
,
05:42
[PATCH v2 11/25] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer
,
Bin Meng
,
05:42
[PATCH v2 17/25] hw/sd: ssi-sd: Support multiple block write
,
Bin Meng
,
05:42
[PATCH v2 18/25] hw/sd: ssi-sd: Bump up version ids of VMStateDescription
,
Bin Meng
,
05:42
[PATCH v2 10/25] hw/sd: ssi-sd: Support multiple block read
,
Bin Meng
,
05:41
[PATCH v2 08/25] hw/sd: ssi-sd: Add a state representing Nac
,
Bin Meng
,
05:41
[PATCH v2 09/25] hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION
,
Bin Meng
,
05:41
[PATCH v2 12/25] hw/sd: sd: Remove duplicated codes in single/multiple block read/write
,
Bin Meng
,
05:41
[PATCH v2 06/25] util: Add CRC16 (CCITT) calculation routines
,
Bin Meng
,
05:41
[PATCH v2 05/25] hw/sd: sd: Drop sd_crc16()
,
Bin Meng
,
05:41
[PATCH v2 07/25] hw/sd: ssi-sd: Suffix a data block with CRC16
,
Bin Meng
,
05:41
[PATCH v2 04/25] hw/sd: sd: Support CMD59 for SPI mode
,
Bin Meng
,
05:41
[PATCH v2 03/25] hw/sd: ssi-sd: Fix incorrect card response sequence
,
Bin Meng
,
05:41
[PATCH v2 01/25] hw/block: m25p80: Add ISSI SPI flash support
,
Bin Meng
,
05:41
[PATCH v2 00/25] hw/riscv: sifive_u: Add missing SPI support
,
Bin Meng
,
05:40
[PATCH v2 02/25] hw/block: m25p80: Add various ISSI flash information
,
Bin Meng
,
05:40
January 22, 2021
Re: [PATCH 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system
,
Alistair Francis
,
16:27
Re: [PATCH 2/4] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
,
Alistair Francis
,
16:23
Re: [PATCH 1/4] hw/riscv: Drop 'struct MemmapEntry'
,
Alistair Francis
,
16:22
[PATCH 4/4] hw/riscv: virt: Map high mmio for PCIe
,
Bin Meng
,
07:30
[PATCH 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system
,
Bin Meng
,
07:30
[PATCH 2/4] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
,
Bin Meng
,
07:30
[PATCH 1/4] hw/riscv: Drop 'struct MemmapEntry'
,
Bin Meng
,
07:30
[PATCH 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine
,
Bin Meng
,
07:30
January 21, 2021
Re: [PATCH v7 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
,
Richard Henderson
,
14:45
Re: [PATCH v7 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Richard Henderson
,
14:42
Re: [RFC v4 08/16] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
,
Richard Henderson
,
14:32
Re: [PATCH v2 1/1] linux-user/signal: Decode waitid si_code
,
Andreas K . Hüttel
,
10:15
January 20, 2021
Re: [PATCH v2 1/1] linux-user/signal: Decode waitid si_code
,
Andreas K . Hüttel
,
15:12
Re: [PATCH] roms/opensbi: Upgrade from v0.8 to v0.9
,
Alistair Francis
,
11:50
January 19, 2021
Re: [PATCH] roms/opensbi: Upgrade from v0.8 to v0.9
,
Alistair Francis
,
20:23
[PATCH] roms/opensbi: Upgrade from v0.8 to v0.9
,
Bin Meng
,
18:45
Re: [PATCH v1 1/1] riscv: Pass RISCVHartArrayState by pointer
,
Eric Blake
,
16:50
Re: [PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
,
Alistair Francis
,
14:23
Re: [PATCH v6 21/72] target/riscv: rvv-1.0: fault-only-first unit stride load
,
Alistair Francis
,
14:20
Re: [PATCH] hw/misc: sifive_u_otp: Use error_report() when block operation fails
,
Alistair Francis
,
14:16
Re: [PATCH v6 00/72] support vector extension v1.0
,
Alistair Francis
,
14:12
Re: [PATCH v6 19/72] target/riscv: rvv-1.0: index load and store instructions
,
Alistair Francis
,
14:10
Re: [PATCH v6 18/72] target/riscv: rvv-1.0: stride load and store instructions
,
Alistair Francis
,
14:04
Re: [PATCH v6 17/72] target/riscv: rvv-1.0: configure instructions
,
Alistair Francis
,
14:00
Re: [PATCH v6 16/72] target/riscv: rvv:1.0: add translation-time nan-box helper function
,
Alistair Francis
,
13:59
Re: [PATCH v6 15/72] target/riscv: introduce more imm value modes in translator functions
,
Alistair Francis
,
13:55
Re: [PATCH v6 13/72] target/riscv: rvv-1.0: add VMA and VTA
,
Alistair Francis
,
13:51
Re: [PATCH v6 06/72] target/riscv: rvv-1.0: add translation-time vector context status
,
Alistair Francis
,
13:48
Re: [PATCH v6 12/72] target/riscv: rvv-1.0: add fractional LMUL
,
Alistair Francis
,
13:44
[PATCH v2 1/1] linux-user/signal: Decode waitid si_code
,
Alistair Francis
,
13:25
Re: [PATCH v6 11/72] target/riscv: rvv-1.0: remove MLEN calculations
,
Alistair Francis
,
12:42
Re: [PATCH v6 10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
,
Alistair Francis
,
12:41
Re: [PATCH v6 09/72] target/riscv: rvv-1.0: add vlenb register
,
Alistair Francis
,
12:40
Re: [PATCH v6 08/72] target/riscv: rvv-1.0: add vcsr register
,
Alistair Francis
,
12:38
Re: [PATCH v1 1/1] linux-user/signal: Decode waitid si_code
,
Alistair Francis
,
12:35
Re: [PATCH] hw/misc: sifive_u_otp: Use error_report() when block operation fails
,
Alistair Francis
,
12:11
Re: [PATCH] target/riscv: Declare csr_ops[] with a known size
,
Alistair Francis
,
12:08
Re: [PATCH v6 07/72] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
,
Alistair Francis
,
11:48
Re: [PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field
,
Alistair Francis
,
11:37
Re: [PATCH v6 04/72] target/riscv: rvv-1.0: add sstatus VS field
,
Alistair Francis
,
11:37
Re: [PATCH v6 03/72] target/riscv: rvv-1.0: add mstatus VS field
,
Alistair Francis
,
11:36
Re: [PATCH v6 02/72] target/riscv: Use FIELD_EX32() to extract wd field
,
Alistair Francis
,
11:35
Re: [PATCH] target/riscv: Declare csr_ops[] with a known size
,
Alistair Francis
,
11:33
January 18, 2021
Re: [PATCH] hw/misc: sifive_u_otp: Use error_report() when block operation fails
,
Philippe Mathieu-Daudé
,
23:25
[PATCH] hw/misc: sifive_u_otp: Use error_report() when block operation fails
,
Bin Meng
,
22:23
Re: [PATCH] target/riscv: Declare csr_ops[] with a known size
,
Philippe Mathieu-Daudé
,
22:00
[PATCH] target/riscv: Declare csr_ops[] with a known size
,
Bin Meng
,
21:52
Re: [PATCH 1/4] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
,
Bin Meng
,
21:41
Re: [PATCH 1/4] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
,
Richard Henderson
,
12:55
Re: [PATCH v1 1/1] riscv: Pass RISCVHartArrayState by pointer
,
Richard Henderson
,
12:14
Re: [PATCH v1 1/1] linux-user/signal: Decode waitid si_code
,
Laurent Vivier
,
09:36
January 17, 2021
Re: [PATCH v1 1/1] riscv: Pass RISCVHartArrayState by pointer
,
Philippe Mathieu-Daudé
,
11:52
January 16, 2021
Re: [PATCH v1 1/1] riscv: Pass RISCVHartArrayState by pointer
,
Alistair Francis
,
17:39
Re: [PATCH v1 1/1] riscv: Pass RISCVHartArrayState by pointer
,
Philippe Mathieu-Daudé
,
17:32
Re: [PATCH v1 1/1] riscv: Pass RISCVHartArrayState by pointer
,
Alistair Francis
,
13:56
Re: [PATCH v2 2/2] target/riscv: Remove built-in GDB XML files for CSRs
,
Alistair Francis
,
13:55
Re: [PATCH v1 1/1] riscv: Pass RISCVHartArrayState by pointer
,
Alistair Francis
,
12:51
Re: [PATCH v1 1/1] riscv: Pass RISCVHartArrayState by pointer
,
Bin Meng
,
11:30
[PATCH v2 2/2] target/riscv: Remove built-in GDB XML files for CSRs
,
Bin Meng
,
00:42
[PATCH v2 1/2] target/riscv: Generate the GDB XML file for CSR registers dynamically
,
Bin Meng
,
00:41
[PATCH v2 0/2] target/riscv: Generate the GDB XML file for CSR registers dynamically
,
Bin Meng
,
00:41
January 15, 2021
Re: [PATCH 3/4] target/riscv: Generate the GDB XML file for CSR registers dynamically
,
Bin Meng
,
20:36
Re: [PATCH v1 1/1] riscv: Pass RISCVHartArrayState by pointer
,
Palmer Dabbelt
,
18:04
Re: [PATCH v1 1/1] linux-user/signal: Decode waitid si_code
,
Alistair Francis
,
18:01
[PATCH v1 1/1] riscv: Pass RISCVHartArrayState by pointer
,
Alistair Francis
,
18:00
Re: [PATCH v7 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
,
Alistair Francis
,
17:10
Re: [PATCH v7 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
,
Alistair Francis
,
17:10
Re: [PATCH v7 1/6] [RISCV_PM] Add J-extension into RISC-V
,
Alistair Francis
,
17:09
Re: [PATCH 3/4] target/riscv: Generate the GDB XML file for CSR registers dynamically
,
Alistair Francis
,
17:08
Re: [PATCH 4/4] target/riscv: Remove built-in GDB XML files for CSRs
,
Alistair Francis
,
17:01
Re: [PATCH 3/4] target/riscv: Generate the GDB XML file for CSR registers dynamically
,
Alistair Francis
,
17:00
Re: [PATCH 2/4] target/riscv: Add CSR name in the CSR function table
,
Alistair Francis
,
16:53
Re: [PATCH 2/4] target/riscv: Add CSR name in the CSR function table
,
Alistair Francis
,
16:52
Re: [PATCH 1/4] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
,
Alistair Francis
,
16:49
Re: [PATCH v3 1/1] target-riscv: support QMP dump-guest-memory
,
Andrew Jones
,
09:45
Re: [PATCH 2/4] target/riscv: Add CSR name in the CSR function table
,
Bin Meng
,
08:43
[PULL 26/30] riscv: Add semihosting support
,
Alex Bennée
,
08:33
Re: [PATCH 2/4] target/riscv: Add CSR name in the CSR function table
,
Alexander Richardson
,
08:15
January 14, 2021
Re: [PATCH v3 1/1] target-riscv: support QMP dump-guest-memory
,
Palmer Dabbelt
,
21:12
RE: [PATCH v2 1/1] target-riscv: support QMP dump-guest-memory
,
Jiangyifei
,
20:36
[PATCH v3 0/1] target-riscv: support QMP dump-guest-memory
,
Yifei Jiang
,
20:29
[PATCH v3 1/1] target-riscv: support QMP dump-guest-memory
,
Yifei Jiang
,
20:28
Re: [PATCH] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
,
Alistair Francis
,
15:34
Re: [PATCH] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
,
Alistair Francis
,
15:21
Re: [PATCH 06/22] util: Add CRC16 (CCITT) calculation routines
,
Alistair Francis
,
15:21
Re: [PATCH 05/22] hw/sd: sd: Drop sd_crc16()
,
Philippe Mathieu-Daudé
,
06:52
Re: [PATCH 13/22] hw/sd: Introduce receive_ready() callback
,
Philippe Mathieu-Daudé
,
06:44
Re: [PATCH 09/22] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer
,
Philippe Mathieu-Daudé
,
06:40
Re: [PATCH v2 3/6] tcg/ppc: Hoist common argument loads in tcg_out_op()
,
Philippe Mathieu-Daudé
,
04:59
January 13, 2021
Re: [PATCH v2 3/6] tcg/ppc: Hoist common argument loads in tcg_out_op()
,
Richard Henderson
,
19:29
Re: [PATCH 22/22] docs/system: riscv: Add documentation for sifive_u machine
,
Alistair Francis
,
19:12
Re: [PATCH 21/22] docs/system: Add RISC-V documentation
,
Alistair Francis
,
19:12
Re: [PATCH 0/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements
,
Richard Henderson
,
13:35
Re: [PATCH 20/22] docs/system: Sort targets in alphabetical order
,
Alistair Francis
,
13:34
Re: [PATCH 19/22] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
,
Alistair Francis
,
13:33
Re: [PATCH 18/22] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
,
Alistair Francis
,
13:33
Re: [PATCH 17/22] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
,
Alistair Francis
,
13:31
Re: [PATCH 16/22] hw/ssi: Add SiFive SPI controller support
,
Alistair Francis
,
13:29
Re: [PATCH 15/22] hw/sd: ssi-sd: Support multiple block write
,
Alistair Francis
,
13:11
Re: [PATCH 14/22] hw/sd: ssi-sd: Support single block write
,
Alistair Francis
,
13:08
Re: [PATCH 12/22] hw/sd: sd.h: Cosmetic change of using spaces
,
Alistair Francis
,
12:59
[PATCH v2 6/6] tcg: Restrict tcg_out_vec_op() to arrays of TCG_MAX_OP_ARGS elements
,
Philippe Mathieu-Daudé
,
12:26
[PATCH v2 4/6] tcg/s390: Hoist common argument loads in tcg_out_op()
,
Philippe Mathieu-Daudé
,
12:26
[PATCH v2 3/6] tcg/ppc: Hoist common argument loads in tcg_out_op()
,
Philippe Mathieu-Daudé
,
12:26
[PATCH v2 5/6] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements
,
Philippe Mathieu-Daudé
,
12:26
[PATCH v2 2/6] tcg/arm: Replace goto statement by fall through comment
,
Philippe Mathieu-Daudé
,
12:25
[PATCH v2 1/6] tcg/arm: Hoist common argument loads in tcg_out_op()
,
Philippe Mathieu-Daudé
,
12:25
[PATCH v2 0/6] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements
,
Philippe Mathieu-Daudé
,
12:25
Re: [PATCH 13/22] hw/sd: Introduce receive_ready() callback
,
Alistair Francis
,
12:22
Re: [PATCH 11/22] hw/sd: sd: Allow single/multiple block write for SPI mode
,
Alistair Francis
,
12:03
Re: [PATCH 10/22] hw/sd: sd: Remove duplicated codes in single/multiple block read/write
,
Alistair Francis
,
12:03
Re: [PATCH 09/22] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer
,
Alistair Francis
,
12:01
Re: [PATCH 08/22] hw/sd: ssi-sd: Support multiple block read (CMD18)
,
Alistair Francis
,
12:00
Re: [PATCH 07/22] hw/sd: ssi-sd: Suffix a data block with CRC16
,
Alistair Francis
,
11:55
Re: [PATCH 2/5] tcg/ppc: Hoist common argument loads in tcg_out_op()
,
Philippe Mathieu-Daudé
,
10:49
Re: [PATCH 2/5] tcg/ppc: Hoist common argument loads in tcg_out_op()
,
Philippe Mathieu-Daudé
,
10:25
Re: [PATCH 0/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements
,
Philippe Mathieu-Daudé
,
10:07
Re: [PATCH 3/5] tcg/s390: Hoist common argument loads in tcg_out_op()
,
Miroslav Rezanina
,
06:57
[RFC v4 16/16] target/riscv: rvb: support and turn on B-extension from command line
,
frank . chang
,
02:15
[RFC v4 15/16] target/riscv: rvb: add/shift with prefix zero-extend
,
frank . chang
,
02:15
[RFC v4 14/16] target/riscv: rvb: address calculation
,
frank . chang
,
02:15
[RFC v4 13/16] target/riscv: rvb: generalized or-combine
,
frank . chang
,
02:15
[RFC v4 12/16] target/riscv: rvb: generalized reverse
,
frank . chang
,
02:15
[RFC v4 11/16] target/riscv: rvb: rotate (left/right)
,
frank . chang
,
02:15
[RFC v4 10/16] target/riscv: rvb: shift ones
,
frank . chang
,
02:15
[RFC v4 09/16] target/riscv: rvb: single-bit instructions
,
frank . chang
,
02:15
[RFC v4 08/16] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
,
frank . chang
,
02:14
[RFC v4 07/16] target/riscv: rvb: sign-extend instructions
,
frank . chang
,
02:14
[RFC v4 05/16] target/riscv: rvb: pack two words into one register
,
frank . chang
,
02:14
[RFC v4 06/16] target/riscv: rvb: min/max instructions
,
frank . chang
,
02:14
[RFC v4 04/16] target/riscv: rvb: logic-with-negate
,
frank . chang
,
02:14
[RFC v4 03/16] target/riscv: rvb: count bits set
,
frank . chang
,
02:14
[RFC v4 02/16] target/riscv: rvb: count leading/trailing zeros
,
frank . chang
,
02:14
[RFC v4 01/16] target/riscv: reformat @sh format encoding for B-extension
,
frank . chang
,
02:14
[RFC v4 00/16] support subsets of bitmanip extension
,
frank . chang
,
02:14
January 12, 2021
Re: [PATCH v6 00/72] support vector extension v1.0
,
no-reply
,
06:10
[PATCH v6 72/72] target/riscv: set mstatus.SD bit when writing fp CSRs
,
frank . chang
,
04:45
[PATCH v6 71/72] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
,
frank . chang
,
04:45
[PATCH v6 70/72] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
,
frank . chang
,
04:44
[PATCH v6 69/72] target/riscv: gdb: support vector registers for rv64 & rv32
,
frank . chang
,
04:44
[PATCH v6 68/72] target/riscv: gdb: modify gdb csr xml file to align with csr register map
,
frank . chang
,
04:44
[PATCH v6 66/72] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
,
frank . chang
,
04:44
[PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs
,
frank . chang
,
04:44
[PATCH v6 65/72] target/riscv: rvv-1.0: implement vstart CSR
,
frank . chang
,
04:44
[PATCH v6 64/72] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
,
frank . chang
,
04:44
[PATCH v6 63/72] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
,
frank . chang
,
04:44
[PATCH v6 61/72] target/riscv: rvv-1.0: widening floating-point/integer type-convert
,
frank . chang
,
04:44
[PATCH v6 62/72] target/riscv: add "set round to odd" rounding mode helper function
,
frank . chang
,
04:44
[PATCH v6 60/72] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
,
frank . chang
,
04:44
[PATCH v6 58/72] target/riscv: rvv-1.0: floating-point min/max instructions
,
frank . chang
,
04:44
[PATCH v6 57/72] target/riscv: rvv-1.0: remove integer extract instruction
,
frank . chang
,
04:44
[PATCH v6 59/72] target/riscv: introduce floating-point rounding mode enum
,
frank . chang
,
04:44
[PATCH v6 56/72] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
,
frank . chang
,
04:43
[PATCH v6 55/72] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
,
frank . chang
,
04:43
[PATCH v6 54/72] target/riscv: rvv-1.0: single-width scaling shift instructions
,
frank . chang
,
04:43
[PATCH v6 53/72] target/riscv: rvv-1.0: widening floating-point reduction instructions
,
frank . chang
,
04:43
[PATCH v6 52/72] target/riscv: rvv-1.0: single-width floating-point reduction
,
frank . chang
,
04:43
[PATCH v6 51/72] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
,
frank . chang
,
04:43
[PATCH v6 50/72] target/riscv: rvv-1.0: floating-point slide instructions
,
frank . chang
,
04:43
[PATCH v6 49/72] target/riscv: rvv-1.0: slide instructions
,
frank . chang
,
04:43
[PATCH v6 48/72] target/riscv: rvv-1.0: mask-register logical instructions
,
frank . chang
,
04:43
[PATCH v6 47/72] target/riscv: rvv-1.0: floating-point compare instructions
,
frank . chang
,
04:43
[PATCH v6 46/72] target/riscv: rvv-1.0: integer comparison instructions
,
frank . chang
,
04:43
[PATCH v6 45/72] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
,
frank . chang
,
04:43
[PATCH v6 44/72] target/riscv: rvv-1.0: widening integer multiply-add instructions
,
frank . chang
,
04:43
[PATCH v6 43/72] target/riscv: rvv-1.0: narrowing integer right shift instructions
,
frank . chang
,
04:43
[PATCH v6 42/72] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
,
frank . chang
,
04:42
[PATCH v6 41/72] target/riscv: rvv-1.0: single-width bit shift instructions
,
frank . chang
,
04:42
[PATCH v6 40/72] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
,
frank . chang
,
04:42
[PATCH v6 39/72] target/riscv: rvv-1.0: integer extension instructions
,
frank . chang
,
04:42
[PATCH v6 38/72] target/riscv: rvv-1.0: whole register move instructions
,
frank . chang
,
04:42
[PATCH v6 36/72] target/riscv: rvv-1.0: floating-point move instruction
,
frank . chang
,
04:42
[PATCH v6 37/72] target/riscv: rvv-1.0: floating-point scalar move instructions
,
frank . chang
,
04:42
[PATCH v6 35/72] target/riscv: rvv-1.0: integer scalar move instructions
,
frank . chang
,
04:42
[PATCH v6 33/72] target/riscv: rvv-1.0: allow load element with sign-extended
,
frank . chang
,
04:42
[PATCH v6 34/72] target/riscv: rvv-1.0: register gather instructions
,
frank . chang
,
04:42
[PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction
,
frank . chang
,
04:42
[PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction
,
frank . chang
,
04:42
[PATCH v6 30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions
,
frank . chang
,
04:42
[PATCH v6 29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction
,
frank . chang
,
04:42
[PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction
,
frank . chang
,
04:42
[PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions
,
frank . chang
,
04:41
[PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction
,
frank . chang
,
04:41
[PATCH v6 22/72] target/riscv: rvv-1.0: amo operations
,
frank . chang
,
04:41
[PATCH v6 25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
,
frank . chang
,
04:41
[PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
,
frank . chang
,
04:41
[PATCH v6 23/72] target/riscv: rvv-1.0: load/store whole register instructions
,
frank . chang
,
04:41
[PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
,
frank . chang
,
04:41
[PATCH v6 21/72] target/riscv: rvv-1.0: fault-only-first unit stride load
,
frank . chang
,
04:41
[PATCH v6 19/72] target/riscv: rvv-1.0: index load and store instructions
,
frank . chang
,
04:41
[PATCH v6 18/72] target/riscv: rvv-1.0: stride load and store instructions
,
frank . chang
,
04:41
[PATCH v6 17/72] target/riscv: rvv-1.0: configure instructions
,
frank . chang
,
04:41
[PATCH v6 16/72] target/riscv: rvv:1.0: add translation-time nan-box helper function
,
frank . chang
,
04:41
[PATCH v6 14/72] target/riscv: rvv-1.0: update check functions
,
frank . chang
,
04:41
[PATCH v6 15/72] target/riscv: introduce more imm value modes in translator functions
,
frank . chang
,
04:41
[PATCH v6 13/72] target/riscv: rvv-1.0: add VMA and VTA
,
frank . chang
,
04:41
[PATCH v6 12/72] target/riscv: rvv-1.0: add fractional LMUL
,
frank . chang
,
04:40
[PATCH v6 11/72] target/riscv: rvv-1.0: remove MLEN calculations
,
frank . chang
,
04:40
[PATCH v6 10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
,
frank . chang
,
04:40
[PATCH v6 09/72] target/riscv: rvv-1.0: add vlenb register
,
frank . chang
,
04:40
[PATCH v6 07/72] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
,
frank . chang
,
04:40
[PATCH v6 08/72] target/riscv: rvv-1.0: add vcsr register
,
frank . chang
,
04:40
[PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field
,
frank . chang
,
04:40
[PATCH v6 06/72] target/riscv: rvv-1.0: add translation-time vector context status
,
frank . chang
,
04:40
[PATCH v6 04/72] target/riscv: rvv-1.0: add sstatus VS field
,
frank . chang
,
04:40
[PATCH v6 03/72] target/riscv: rvv-1.0: add mstatus VS field
,
frank . chang
,
04:40
[PATCH v6 02/72] target/riscv: Use FIELD_EX32() to extract wd field
,
frank . chang
,
04:40
[PATCH v6 01/72] target/riscv: drop vector 0.7.1 and add 1.0 support
,
frank . chang
,
04:40
[PATCH v6 00/72] support vector extension v1.0
,
frank . chang
,
04:40
Re: [RFC v3 16/16] target/riscv: rvb: support and turn on B-extension from command line
,
Richard Henderson
,
00:47
Re: [RFC v3 13/16] target/riscv: rvb: generalized or-combine
,
Richard Henderson
,
00:47
Re: [RFC v3 04/16] target/riscv: rvb: logic-with-negate
,
Richard Henderson
,
00:46
Re: [RFC v3 11/16] target/riscv: rvb: rotate (left/right)
,
Richard Henderson
,
00:46
Re: [RFC v3 08/16] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
,
Frank Chang
,
00:27
January 11, 2021
Re: [RFC v3 09/16] target/riscv: rvb: single-bit instructions
,
Richard Henderson
,
23:56
Re: [RFC v3 08/16] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
,
Richard Henderson
,
23:55
[PATCH 4/4] target/riscv: Remove built-in GDB XML files for CSRs
,
Bin Meng
,
23:52
[PATCH 3/4] target/riscv: Generate the GDB XML file for CSR registers dynamically
,
Bin Meng
,
23:52
[PATCH 2/4] target/riscv: Add CSR name in the CSR function table
,
Bin Meng
,
23:52
[PATCH 1/4] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
,
Bin Meng
,
23:52
[PATCH 0/4] target/riscv: Generate the GDB XML file for CSR registers dynamically
,
Bin Meng
,
23:52
[RFC v3 16/16] target/riscv: rvb: support and turn on B-extension from command line
,
frank . chang
,
21:21
[RFC v3 15/16] target/riscv: rvb: add/shift with prefix zero-extend
,
frank . chang
,
21:21
[RFC v3 14/16] target/riscv: rvb: address calculation
,
frank . chang
,
21:21
[RFC v3 13/16] target/riscv: rvb: generalized or-combine
,
frank . chang
,
21:21
[RFC v3 12/16] target/riscv: rvb: generalized reverse
,
frank . chang
,
21:21
[RFC v3 11/16] target/riscv: rvb: rotate (left/right)
,
frank . chang
,
21:21
[RFC v3 10/16] target/riscv: rvb: shift ones
,
frank . chang
,
21:21
[RFC v3 09/16] target/riscv: rvb: single-bit instructions
,
frank . chang
,
21:21
[RFC v3 07/16] target/riscv: rvb: sign-extend instructions
,
frank . chang
,
21:21
[RFC v3 08/16] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
,
frank . chang
,
21:21
[RFC v3 06/16] target/riscv: rvb: min/max instructions
,
frank . chang
,
21:21
[RFC v3 05/16] target/riscv: rvb: pack two words into one register
,
frank . chang
,
21:20
[RFC v3 04/16] target/riscv: rvb: logic-with-negate
,
frank . chang
,
21:20
[RFC v3 03/16] target/riscv: rvb: count bits set
,
frank . chang
,
21:20
[RFC v3 02/16] target/riscv: rvb: count leading/trailing zeros
,
frank . chang
,
21:20
[RFC v3 01/16] target/riscv: reformat @sh format encoding for B-extension
,
frank . chang
,
21:20
[RFC v3 00/16] support subsets of bitmanip extension
,
frank . chang
,
21:20
Re: [RFC PATCH 4/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements
,
Miroslav Rezanina
,
14:19
Re: [PATCH 0/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements
,
Richard Henderson
,
12:23
[RFC PATCH 5/5] tcg: Restrict tcg_out_vec_op() to arrays of TCG_MAX_OP_ARGS elements
,
Philippe Mathieu-Daudé
,
10:01
[RFC PATCH 4/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements
,
Philippe Mathieu-Daudé
,
10:01
[PATCH 3/5] tcg/s390: Hoist common argument loads in tcg_out_op()
,
Philippe Mathieu-Daudé
,
10:01
[PATCH 1/5] tcg/arm: Hoist common argument loads in tcg_out_op()
,
Philippe Mathieu-Daudé
,
10:01
[PATCH 2/5] tcg/ppc: Hoist common argument loads in tcg_out_op()
,
Philippe Mathieu-Daudé
,
10:01
[PATCH 0/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements
,
Philippe Mathieu-Daudé
,
10:01
January 10, 2021
[PATCH v7 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
,
Alexey Baturo
,
13:51
[PATCH v7 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
,
Alexey Baturo
,
13:51
[PATCH v7 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the ones required for hypervisor mode
,
Alexey Baturo
,
13:51
[PATCH v7 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
,
Alexey Baturo
,
13:51
[PATCH v7 0/6] RISC-V Pointer Masking implementation
,
Alexey Baturo
,
13:51
[PATCH v7 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Alexey Baturo
,
13:51
[PATCH v7 1/6] [RISCV_PM] Add J-extension into RISC-V
,
Alexey Baturo
,
13:51
January 09, 2021
Re: [PATCH] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
,
Philippe Mathieu-Daudé
,
18:44
Re: [PATCH v2 1/1] target-riscv: support QMP dump-guest-memory
,
Andrew Jones
,
18:25
[PATCH] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
,
Bin Meng
,
09:36
January 08, 2021
Re: [PATCH v1 16/20] riscv: Add semihosting support
,
Keith Packard
,
19:44
Re: [PATCH v2] target/riscv/pmp: Raise exception if no PMP entry is configured
,
Alistair Francis
,
18:34
Re: [PATCH v1 16/20] riscv: Add semihosting support
,
Alistair Francis
,
18:31
[PATCH v1 16/20] riscv: Add semihosting support
,
Alex Bennée
,
17:52
Re: [PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0
,
Alex Bennée
,
17:33
January 07, 2021
Re: [PATCH v2] target/riscv/pmp: Raise exception if no PMP entry is configured
,
Atish Patra
,
14:02
Re: [PATCH v2 1/1] target-riscv: support QMP dump-guest-memory
,
Alistair Francis
,
12:21
Re: [PATCH v2] target/riscv/pmp: Raise exception if no PMP entry is configured
,
Alistair Francis
,
12:20
[PATCH 3/9] semihosting: Change internal common-semi interfaces to use CPUState *
,
Keith Packard
,
12:18
[PATCH 6/9] riscv: Add semihosting support for user mode
,
Keith Packard
,
12:18
[PATCH 2/9] semihosting: Change common-semi API to be architecture-independent
,
Keith Packard
,
12:14
[PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set
,
Keith Packard
,
12:14
[PATCH 8/9] semihosting: Implement SYS_TMPNAM
,
Keith Packard
,
12:14
Re: [v2 PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB
,
Alistair Francis
,
12:14
[PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0
,
Keith Packard
,
12:14
[PATCH 7/9] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ
,
Keith Packard
,
12:14
[PATCH 9/9] semihosting: Implement SYS_ISERROR
,
Keith Packard
,
12:14
[PATCH 1/9] semihosting: Move ARM semihosting code to shared directories
,
Keith Packard
,
12:14
[PATCH 5/9] riscv: Add semihosting support
,
Keith Packard
,
12:13
Re: [PATCH v4] gdb: riscv: Add target description
,
Alistair Francis
,
12:12
[v2 PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB
,
Atish Patra
,
04:11
Re: [PATCH v4] gdb: riscv: Add target description
,
Philippe Mathieu-Daudé
,
01:56
January 06, 2021
[PATCH v4] gdb: riscv: Add target description
,
Sylvain Pelissier
,
15:41
Re: [PATCH v2] gdb: riscv: Add target description
,
Alex Bennée
,
06:40
Re: [PATCH v3] gdb: riscv: Add target description
,
Bin Meng
,
05:57
Re: [PATCH v2] gdb: riscv: Add target description
,
Sylvain Pelissier
,
05:49
[PATCH v3] gdb: riscv: Add target description
,
Sylvain Pelissier
,
05:33
January 05, 2021
Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB
,
Atish Patra
,
21:14
Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB
,
Bin Meng
,
19:04
Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB
,
Atish Patra
,
18:44
Re: [PATCH 02/22] hw/block: m25p80: Add various ISSI flash information
,
Alistair Francis
,
16:16
Re: [PATCH v2] gdb: riscv: Add target description
,
Alistair Francis
,
16:04
Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB
,
Alistair Francis
,
16:03
Re: [PATCH v2] gdb: riscv: Add target description
,
Alistair Francis
,
15:34
Re: [PATCH RFC v4 13/15] target/riscv: Introduce dynamic time frequency for virt machine
,
Alistair Francis
,
12:37
January 04, 2021
Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB
,
Bin Meng
,
22:11
Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB
,
Bin Meng
,
22:06
Re: [PATCH 01/22] hw/block: m25p80: Add ISSI SPI flash support
,
Bin Meng
,
18:31
Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB
,
Atish Patra
,
15:24
Re: [PATCH 01/22] hw/block: m25p80: Add ISSI SPI flash support
,
Francisco Iglesias
,
11:58
January 02, 2021
Re: [PATCH 05/22] hw/sd: sd: Drop sd_crc16()
,
Pragnesh Patel
,
08:53
Re: [PATCH 04/22] hw/sd: sd: Support CMD59 for SPI mode
,
Pragnesh Patel
,
08:51
Re: [PATCH 03/22] hw/sd: ssi-sd: Fix incorrect card response sequence
,
Pragnesh Patel
,
08:49
Re: [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support
,
Bin Meng
,
08:36
Re: [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support
,
Pragnesh Patel
,
08:30
Re: [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support
,
Bin Meng
,
08:16
Re: [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support
,
Pragnesh Patel
,
07:27
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