Re: [PATCH v6 07/72] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers

[Alistair Francis]

On Tue, Jan 12, 2021 at 1:50 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> * Remove VXRM and VXSAT fields from FCSR register as they are only
>   presented in VCSR register.
> * Remove RVV loose check in fs() predicate function.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 13 -------------
>  1 file changed, 13 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c8b1e4954ec..6eda5bacb7c 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -46,10 +46,6 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations 
> *ops)
>  static int fs(CPURISCVState *env, int csrno)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    /* loose check condition for fcsr in vector extension */
> -    if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
> -        return 0;
> -    }
>      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
>          return -RISCV_EXCP_ILLEGAL_INST;
>      }
> @@ -254,10 +250,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, 
> target_ulong *val)
>  #endif
>      *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
>          | (env->frm << FSR_RD_SHIFT);
> -    if (vs(env, csrno) >= 0) {
> -        *val |= (env->vxrm << FSR_VXRM_SHIFT)
> -                | (env->vxsat << FSR_VXSAT_SHIFT);
> -    }
>      return 0;
>  }
>
> @@ -268,13 +260,8 @@ static int write_fcsr(CPURISCVState *env, int csrno, 
> target_ulong val)
>          return -RISCV_EXCP_ILLEGAL_INST;
>      }
>      env->mstatus |= MSTATUS_FS;
> -    env->mstatus |= MSTATUS_VS;
>  #endif
>      env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> -    if (vs(env, csrno) >= 0) {
> -        env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
> -        env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
> -    }
>      riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
>      return 0;
>  }
> --
> 2.17.1
>
>