Archives are refreshed every 15 minutes - for details, please visit
the main index
.
You can also
download the archives in mbox format
.
qemu-riscv (date)
[
Thread Index
][
Top
][
All Lists
][
qemu-riscv info page
]
Advanced
[
Prev Period
]
Last Modified: Sun Feb 28 2021 06:44:44 -0500
Messages in reverse chronological order
[
Next Period
]
February 28, 2021
Re: [PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt
,
Bin Meng
,
06:44
Re: [PATCH v2 1/2] hw/riscv: Add fw_cfg support to virt
,
Bin Meng
,
06:42
Re: [PATCH v2 1/2] hw/riscv: Add fw_cfg support to virt
,
Asherah Connor
,
06:18
[PATCH v3 2/2] hw/riscv: allow ramfb on virt
,
Asherah Connor
,
06:17
[PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt
,
Asherah Connor
,
06:17
[PATCH v3 0/2] hw/riscv: Add fw_cfg support, allow ramfb
,
Asherah Connor
,
06:17
Re: [PATCH v2 2/2] hw/riscv: allow ramfb on virt
,
Bin Meng
,
01:11
Re: [PATCH v2 1/2] hw/riscv: Add fw_cfg support to virt
,
Bin Meng
,
01:06
Re: [PATCH v3 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine
,
Bin Meng
,
00:15
February 27, 2021
Re: [PATCH 07/16] cpu: Introduce CPUSystemOperations structure
,
Claudio Fontana
,
14:12
Re: [PATCH 07/16] cpu: Introduce CPUSystemOperations structure
,
Claudio Fontana
,
14:12
February 26, 2021
[PATCH 16/16] cpu: Restrict cpu_paging_enabled / cpu_get_memory_mapping to sysemu
,
Philippe Mathieu-Daudé
,
11:34
[PATCH 15/16] cpu: Move CPUClass::get_paging_enabled to CPUSystemOperations
,
Philippe Mathieu-Daudé
,
11:34
[PATCH 14/16] cpu: Move CPUClass::get_memory_mapping to CPUSystemOperations
,
Philippe Mathieu-Daudé
,
11:34
[PATCH 13/16] cpu: Move CPUClass::get_phys_page_debug to CPUSystemOperations
,
Philippe Mathieu-Daudé
,
11:34
[PATCH 12/16] cpu: Move CPUClass::asidx_from_attrs to CPUSystemOperations
,
Philippe Mathieu-Daudé
,
11:34
[PATCH 11/16] cpu: Move CPUClass::write_elf* to CPUSystemOperations
,
Philippe Mathieu-Daudé
,
11:34
[PATCH 08/16] cpu: Move CPUClass::vmsd to CPUSystemOperations
,
Philippe Mathieu-Daudé
,
11:34
[PATCH 10/16] cpu: Move CPUClass::get_crash_info to CPUSystemOperations
,
Philippe Mathieu-Daudé
,
11:34
[PATCH 09/16] cpu: Move CPUClass::virtio_is_big_endian to CPUSystemOperations
,
Philippe Mathieu-Daudé
,
11:34
[PATCH 07/16] cpu: Introduce CPUSystemOperations structure
,
Philippe Mathieu-Daudé
,
11:33
[PATCH 06/16] cpu: Directly use get_memory_mapping() fallback handlers in place
,
Philippe Mathieu-Daudé
,
11:33
[PATCH 05/16] cpu: Directly use get_paging_enabled() fallback handlers in place
,
Philippe Mathieu-Daudé
,
11:33
[PATCH 04/16] cpu: Directly use cpu_write_elf*() fallback handlers in place
,
Philippe Mathieu-Daudé
,
11:33
[PATCH 03/16] cpu: Introduce cpu_virtio_is_big_endian()
,
Philippe Mathieu-Daudé
,
11:32
[PATCH 02/16] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
,
Philippe Mathieu-Daudé
,
11:32
[PATCH 01/16] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
,
Philippe Mathieu-Daudé
,
11:32
[PATCH 00/16] cpu: Introduce CPUSystemOperations structure
,
Philippe Mathieu-Daudé
,
11:32
[PATCH 2/2] semihosting: Move hw/semihosting/ -> semihosting/
,
Philippe Mathieu-Daudé
,
08:14
[PATCH 1/2] semihosting: Move include/hw/semihosting/ -> include/semihosting/
,
Philippe Mathieu-Daudé
,
08:14
[PATCH 0/2] semihosting: Move it out of hw/
,
Philippe Mathieu-Daudé
,
08:14
February 25, 2021
[PATCH v2 2/2] hw/riscv: allow ramfb on virt
,
Asherah Connor
,
22:55
[PATCH v2 1/2] hw/riscv: Add fw_cfg support to virt
,
Asherah Connor
,
22:55
[PATCH v2 0/2] hw/riscv: Add fw_cfg support, allow ramfb
,
Asherah Connor
,
22:55
[PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
,
frank . chang
,
22:26
[PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
,
frank . chang
,
22:26
[PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction
,
frank . chang
,
22:25
[PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
,
frank . chang
,
22:25
[PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs
,
frank . chang
,
22:25
[PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
,
frank . chang
,
22:25
[PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
,
frank . chang
,
22:25
[PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32
,
frank . chang
,
22:25
[PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs
,
frank . chang
,
22:25
[PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
,
frank . chang
,
22:25
[PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR
,
frank . chang
,
22:25
[PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
,
frank . chang
,
22:25
[PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
,
frank . chang
,
22:25
[PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function
,
frank . chang
,
22:25
[PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert
,
frank . chang
,
22:25
[PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
,
frank . chang
,
22:25
[PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum
,
frank . chang
,
22:24
[PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions
,
frank . chang
,
22:24
[PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction
,
frank . chang
,
22:24
[PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
,
frank . chang
,
22:24
[PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
,
frank . chang
,
22:24
[PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions
,
frank . chang
,
22:24
[PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions
,
frank . chang
,
22:24
[PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction
,
frank . chang
,
22:24
[PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
,
frank . chang
,
22:24
[PATCH v7 50/75] target/riscv: rvv-1.0: floating-point slide instructions
,
frank . chang
,
22:24
[PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions
,
frank . chang
,
22:24
[PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions
,
frank . chang
,
22:24
[PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions
,
frank . chang
,
22:23
[PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions
,
frank . chang
,
22:23
[PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
,
frank . chang
,
22:23
[PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions
,
frank . chang
,
22:23
[PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions
,
frank . chang
,
22:23
[PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
,
frank . chang
,
22:23
[PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions
,
frank . chang
,
22:23
[PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
,
frank . chang
,
22:23
[PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions
,
frank . chang
,
22:22
[PATCH v7 38/75] target/riscv: rvv-1.0: whole register move instructions
,
frank . chang
,
22:22
[PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions
,
frank . chang
,
22:22
[PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction
,
frank . chang
,
22:22
[PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions
,
frank . chang
,
22:22
[PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions
,
frank . chang
,
22:22
[PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended
,
frank . chang
,
22:22
[PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction
,
frank . chang
,
22:22
[PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction
,
frank . chang
,
22:22
[PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions
,
frank . chang
,
22:22
[PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction
,
frank . chang
,
22:22
[PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction
,
frank . chang
,
22:22
[PATCH v7 27/75] target/riscv: rvv-1.0: floating-point classify instructions
,
frank . chang
,
22:21
[PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction
,
frank . chang
,
22:21
[PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
,
frank . chang
,
22:21
[PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
,
frank . chang
,
22:21
[PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions
,
frank . chang
,
22:21
[PATCH v7 22/75] target/riscv: rvv-1.0: amo operations
,
frank . chang
,
22:21
[PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load
,
frank . chang
,
22:21
[PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
,
frank . chang
,
22:21
[PATCH v7 19/75] target/riscv: rvv-1.0: index load and store instructions
,
frank . chang
,
22:21
[PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions
,
frank . chang
,
22:21
[PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions
,
frank . chang
,
22:20
[PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function
,
frank . chang
,
22:20
[PATCH v7 14/75] target/riscv: rvv-1.0: update check functions
,
frank . chang
,
22:20
[PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions
,
frank . chang
,
22:20
[PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA
,
frank . chang
,
22:20
[PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL
,
frank . chang
,
22:20
[PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations
,
frank . chang
,
22:20
[PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
,
frank . chang
,
22:20
[PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register
,
frank . chang
,
22:20
[PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register
,
frank . chang
,
22:20
[PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
,
frank . chang
,
22:20
[PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status
,
frank . chang
,
22:19
[PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field
,
frank . chang
,
22:19
[PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus VS field
,
frank . chang
,
22:19
[PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field
,
frank . chang
,
22:19
[PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field
,
frank . chang
,
22:19
[PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support
,
frank . chang
,
22:19
[PATCH v7 00/75] support vector extension v1.0
,
frank . chang
,
22:19
Re: [PATCH] hw/riscv: Add basic fw_cfg support to virt
,
Asherah Connor
,
10:01
Re: [PATCH] hw/riscv: Add basic fw_cfg support to virt
,
Philippe Mathieu-Daudé
,
06:16
February 23, 2021
Re: [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
,
Frank Chang
,
19:44
Re: [PATCH v2 2/2] target/riscv: Call check_access() before tcg_temp_new()
,
Richard Henderson
,
19:31
Re: [PATCH v2 1/2] target/riscv: Reduce duplicated code in trans_rvh.c.inc
,
Richard Henderson
,
19:24
Re: [PATCH] target/riscv: fix vs() to return proper error code
,
Richard Henderson
,
13:46
Re: [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
,
Richard Henderson
,
13:25
[PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
,
frank . chang
,
03:20
[PATCH] target/riscv: fix vs() to return proper error code
,
frank . chang
,
01:59
February 22, 2021
[PATCH v2 1/2] target/riscv: Reduce duplicated code in trans_rvh.c.inc
,
Alex Richardson
,
13:50
[PATCH v2 2/2] target/riscv: Call check_access() before tcg_temp_new()
,
Alex Richardson
,
13:50
February 21, 2021
[PATCH 3/3] target/riscv: flush TLB pages if PMP permission has been changed
,
Jim Shu
,
09:02
[PATCH 1/3] target/riscv: propagate PMP permission to TLB page
,
Jim Shu
,
09:02
[PATCH 0/3] target/riscv: fix PMP permission checking when softmmu's TLB hits
,
Jim Shu
,
09:02
[PATCH 2/3] target/riscv: add log of PMP permission checking
,
Jim Shu
,
09:02
[PATCH 1/3] target/riscv: propagate PMP permission to TLB page
,
Jim Shu
,
08:34
[PATCH 3/3] target/riscv: flush TLB pages if PMP permission has been changed
,
Jim Shu
,
08:34
[PATCH 2/3] target/riscv: add log of PMP permission checking
,
Jim Shu
,
08:34
February 20, 2021
Re: [PATCH v2 3/6] target/mips: Include missing "tcg/tcg.h" header
,
Philippe Mathieu-Daudé
,
15:08
[PATCH v3 4/4] hw/riscv: virt: Map high mmio for PCIe
,
Bin Meng
,
09:48
[PATCH v3 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system
,
Bin Meng
,
09:48
[PATCH v3 2/4] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
,
Bin Meng
,
09:48
[PATCH v3 1/4] hw/riscv: Drop 'struct MemmapEntry'
,
Bin Meng
,
09:48
[PATCH v3 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine
,
Bin Meng
,
09:48
Re: [PATCH v2 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system
,
Peter Maydell
,
05:37
Re: [PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
,
Frank Chang
,
00:14
February 19, 2021
Re: [PATCH v2 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system
,
Bin Meng
,
21:39
Re: [PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
,
Richard Henderson
,
11:12
[PATCH 2/2] target/riscv: Call check_access() before tcg_temp_new()
,
Alex Richardson
,
10:51
[PATCH 1/2] target/riscv: Reduce duplicated code in trans_rvh.c.inc
,
Alex Richardson
,
10:51
[PATCH v2 4/4] hw/riscv: virt: Map high mmio for PCIe
,
Bin Meng
,
10:39
[PATCH v2 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system
,
Bin Meng
,
10:39
[PATCH v2 2/4] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
,
Bin Meng
,
10:39
[PATCH v2 1/4] hw/riscv: Drop 'struct MemmapEntry'
,
Bin Meng
,
10:39
[PATCH v2 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine
,
Bin Meng
,
10:39
[PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
,
frank . chang
,
04:59
February 18, 2021
Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions
,
Richard Henderson
,
11:21
Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions
,
Richard Henderson
,
11:21
Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions
,
LIU Zhiwei
,
03:48
Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions
,
LIU Zhiwei
,
03:39
February 15, 2021
Re: [PATCH v7 0/6] RISC-V Pointer Masking implementation
,
Alistair Francis
,
19:02
Re: [PATCH v7 0/6] RISC-V Pointer Masking implementation
,
Alexey Baturo
,
15:52
February 14, 2021
single stepping with gdb+qemu does not seem to work on SRET instruction
,
Yann Sionneau
,
14:00
Re: Emulating sd card with hifive_u risc-v machine
,
Bin Meng
,
00:05
February 13, 2021
Re: [PATCH v2 1/1] linux-user/signal: Decode waitid si_code
,
Laurent Vivier
,
11:18
Re: [PATCH v2 1/1] linux-user/signal: Decode waitid si_code
,
Laurent Vivier
,
11:09
February 12, 2021
Re: [PATCH 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine
,
Alistair Francis
,
17:06
Re: [PATCH 4/4] hw/riscv: virt: Map high mmio for PCIe
,
Alistair Francis
,
16:48
Re: [PATCH v2 1/1] linux-user/signal: Decode waitid si_code
,
Alistair Francis
,
16:45
Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions
,
Richard Henderson
,
14:02
Re: [PATCH 03/38] target/riscv: Fixup saturate subtract function
,
Richard Henderson
,
13:52
Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions
,
Richard Henderson
,
13:03
[PATCH 38/38] target/riscv: configure and turn on packed extension from command line
,
LIU Zhiwei
,
11:21
[PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions
,
LIU Zhiwei
,
11:19
[PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
,
LIU Zhiwei
,
11:17
[PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
,
LIU Zhiwei
,
11:15
[PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions
,
LIU Zhiwei
,
11:13
[PATCH 33/38] target/riscv: RV64 Only 32-bit Multiply Instructions
,
LIU Zhiwei
,
11:11
[PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
,
LIU Zhiwei
,
11:09
[PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
,
LIU Zhiwei
,
11:07
[PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions
,
LIU Zhiwei
,
11:05
[PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
,
LIU Zhiwei
,
11:03
[PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions
,
LIU Zhiwei
,
11:01
[PATCH 27/38] target/riscv: 32-bit Computation Instructions
,
LIU Zhiwei
,
10:59
[PATCH 26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions
,
LIU Zhiwei
,
10:57
[PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions
,
LIU Zhiwei
,
10:55
[PATCH 24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
10:53
[PATCH 23/38] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
10:51
[PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
10:49
[PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions
,
LIU Zhiwei
,
10:47
[PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions
,
LIU Zhiwei
,
10:45
[PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
10:43
[PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
,
LIU Zhiwei
,
10:41
[PATCH 17/38] target/riscv: Signed MSW 32x16 Multiply and Add Instructions
,
LIU Zhiwei
,
10:39
[PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions
,
LIU Zhiwei
,
10:37
[PATCH 15/38] target/riscv: 16-bit Packing Instructions
,
LIU Zhiwei
,
10:35
[PATCH 14/38] target/riscv: 8-bit Unpacking Instructions
,
LIU Zhiwei
,
10:33
[PATCH 13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions
,
LIU Zhiwei
,
10:31
[PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions
,
LIU Zhiwei
,
10:29
[PATCH 01/38] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
10:27
[PATCH 11/38] target/riscv: SIMD 8-bit Multiply Instructions
,
LIU Zhiwei
,
10:27
[PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions
,
LIU Zhiwei
,
10:24
[PATCH 09/38] target/riscv: SIMD 8-bit Compare Instructions
,
LIU Zhiwei
,
10:23
[PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions
,
LIU Zhiwei
,
10:21
[PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions
,
LIU Zhiwei
,
10:19
[PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions
,
LIU Zhiwei
,
10:17
[PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction
,
LIU Zhiwei
,
10:15
[PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions
,
LIU Zhiwei
,
10:12
[PATCH 03/38] target/riscv: Fixup saturate subtract function
,
LIU Zhiwei
,
10:10
[PATCH 02/38] target/riscv: Hoist vector functions
,
LIU Zhiwei
,
10:07
[PATCH 00/38] target/riscv: support packed extension v0.9.2
,
LIU Zhiwei
,
10:03
February 11, 2021
[PATCH v2 2/7] hw/riscv: migrate fdt field to generic MachineState
,
Alex Bennée
,
12:20
February 10, 2021
Re: qemu support for rv64imafd/rv64imafdc
,
Billa Surendra
,
20:45
Re: [PATCH v1 1/1] MAINTAINERS: Add a SiFIve machine section
,
Alistair Francis
,
17:33
Re: Emulating sd card with hifive_u risc-v machine
,
Alistair Francis
,
17:28
Re: Emulating sd card with hifive_u risc-v machine
,
Pascal Scholz
,
16:46
Re: qemu support for rv64imafd/rv64imafdc
,
Palmer Dabbelt
,
15:28
Re: [PATCH v2 2/4] Implementation of enhanced PMP(ePMP) support
,
Alistair Francis
,
15:19
Re: [PATCH v2 0/4] riscv: Add enhanced PMP support
,
Alistair Francis
,
15:13
Re: [PATCH v2 3/4] Add ePMP CSR accesses
,
Alistair Francis
,
15:12
qemu support for rv64imafd/rv64imafdc
,
Billa Surendra
,
11:01
February 09, 2021
Re: [PATCH v2 2/4] Implementation of enhanced PMP(ePMP) support
,
Alistair Francis
,
13:26
Re: [PATCH v1 1/1] MAINTAINERS: Add a SiFIve machine section
,
Philippe Mathieu-Daudé
,
04:04
February 08, 2021
Re: [PATCH v1 1/1] MAINTAINERS: Add a SiFIve machine section
,
Palmer Dabbelt
,
21:17
Re: [PATCH v1 1/1] MAINTAINERS: Add a SiFIve machine section
,
Bin Meng
,
21:15
[PATCH v1 1/1] MAINTAINERS: Add a SiFIve machine section
,
Alistair Francis
,
21:11
Re: [PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support
,
Palmer Dabbelt
,
20:53
Re: [PATCH v2 6/7] goldfish_rtc: re-arm the alarm after migration
,
Alistair Francis
,
20:50
Re: [PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support
,
Bin Meng
,
20:47
Re: [PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support
,
Alistair Francis
,
20:44
Re: [PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support
,
Alistair Francis
,
20:39
Re: Emulating sd card with hifive_u risc-v machine
,
Alistair Francis
,
17:50
Re: [RFC PATCH v2 5/6] accel/tcg: Refactor debugging tlb_assert_iotlb_entry_for_ptr_present()
,
Richard Henderson
,
17:34
Re: [RFC PATCH v2 5/6] accel/tcg: Refactor debugging tlb_assert_iotlb_entry_for_ptr_present()
,
Alex Bennée
,
09:51
Re: [PATCH v2 6/6] exec/cpu_ldst: Move tlb* declarations to "exec/exec-all.h"
,
Alex Bennée
,
09:46
Re: [PATCH v2 4/6] accel/tcg: Include missing "tcg/tcg.h" header
,
Alex Bennée
,
09:37
Emulating sd card with hifive_u risc-v machine
,
Pascal Scholz
,
09:35
Re: [RFC PATCH v2 1/6] target: Replace tcg_debug_assert() by assert()
,
Alex Bennée
,
09:02
Re: [RFC PATCH v2 5/6] accel/tcg: Refactor debugging tlb_assert_iotlb_entry_for_ptr_present()
,
Philippe Mathieu-Daudé
,
08:53
Re: [RFC PATCH v2 5/6] accel/tcg: Refactor debugging tlb_assert_iotlb_entry_for_ptr_present()
,
Alex Bennée
,
03:50
February 07, 2021
[PATCH v2 6/6] exec/cpu_ldst: Move tlb* declarations to "exec/exec-all.h"
,
Philippe Mathieu-Daudé
,
18:23
[RFC PATCH v2 5/6] accel/tcg: Refactor debugging tlb_assert_iotlb_entry_for_ptr_present()
,
Philippe Mathieu-Daudé
,
18:23
[PATCH v2 4/6] accel/tcg: Include missing "tcg/tcg.h" header
,
Philippe Mathieu-Daudé
,
18:23
[PATCH v2 2/6] target/m68k: Include missing "tcg/tcg.h" header
,
Philippe Mathieu-Daudé
,
18:23
[PATCH v2 3/6] target/mips: Include missing "tcg/tcg.h" header
,
Philippe Mathieu-Daudé
,
18:23
[RFC PATCH v2 1/6] target: Replace tcg_debug_assert() by assert()
,
Philippe Mathieu-Daudé
,
18:23
[RFC PATCH v2 0/6] exec: Remove "tcg/tcg.h" from "exec/cpu_ldst.h"
,
Philippe Mathieu-Daudé
,
18:23
Re: [PATCH 6/6] exec/cpu_ldst: Move tlb* declarations to "exec/exec-all.h"
,
Philippe Mathieu-Daudé
,
18:20
[PATCH 6/6] exec/cpu_ldst: Move tlb* declarations to "exec/exec-all.h"
,
Philippe Mathieu-Daudé
,
17:58
[RFC PATCH 5/6] accel/tcg: Refactor debugging tlb_assert_iotlb_entry_for_ptr_present()
,
Philippe Mathieu-Daudé
,
17:58
[PATCH 4/6] accel/tcg: Include missing "tcg/tcg.h" header
,
Philippe Mathieu-Daudé
,
17:58
[PATCH 3/6] target/mips: Include missing "tcg/tcg.h" header
,
Philippe Mathieu-Daudé
,
17:58
[PATCH 2/6] target/m68k: Include missing "tcg/tcg.h" header
,
Philippe Mathieu-Daudé
,
17:57
[RFC PATCH 1/6] target: Replace tcg_debug_assert() by assert()
,
Philippe Mathieu-Daudé
,
17:57
[RFC PATCH 0/6] exec: Remove "tcg/tcg.h" from "exec/cpu_ldst.h"
,
Philippe Mathieu-Daudé
,
17:57
February 06, 2021
Re: [PATCH v2 6/7] goldfish_rtc: re-arm the alarm after migration
,
Laurent Vivier
,
09:46
February 04, 2021
Sample Baremetal program with Interrupt
,
vijayvithal jahagirdar
,
16:43
February 03, 2021
Re: [PATCH v7 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
,
Alistair Francis
,
14:28
Re: [PATCH v7 0/6] RISC-V Pointer Masking implementation
,
Alistair Francis
,
14:23
Re: [PATCH v7 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Alistair Francis
,
14:20
Re: [PATCH v7 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the ones required for hypervisor mode
,
Alistair Francis
,
14:20
Re: [PATCH v4 1/1] target-riscv: support QMP dump-guest-memory
,
Alistair Francis
,
13:58
February 01, 2021
Re: [PATCH 09/10] target: Move ARM_COMPATIBLE_SEMIHOSTING feature to target Kconfig
,
Alistair Francis
,
15:00
Re: [PATCH 08/10] default-configs: Remove unnecessary SEMIHOSTING selection
,
Alistair Francis
,
14:59
[PATCH v4 1/1] target-riscv: support QMP dump-guest-memory
,
Yifei Jiang
,
07:45
[PATCH v4 0/1] target-riscv: support QMP dump-guest-memory
,
Yifei Jiang
,
07:45
Re: [PATCH 10/10] target: Move SEMIHOSTING feature to target Kconfig
,
Alex Bennée
,
07:03
Re: [PATCH 09/10] target: Move ARM_COMPATIBLE_SEMIHOSTING feature to target Kconfig
,
Alex Bennée
,
06:55
Re: [PATCH 08/10] default-configs: Remove unnecessary SEMIHOSTING selection
,
Alex Bennée
,
06:53
Re: [PATCH 07/10] target/arm: Move V7M feature to target Kconfig
,
Alex Bennée
,
06:25
Re: [PATCH 05/10] meson: Introduce target-specific Kconfig
,
Alex Bennée
,
06:25
Re: [PATCH 06/10] target/i386: Move SEV feature to target Kconfig
,
Alex Bennée
,
06:24
Re: [PATCH 04/10] hw/lm32/Kconfig: Have MILKYMIST select LM32_PERIPHERALS
,
Alex Bennée
,
06:12
Re: [PATCH 03/10] hw/sh4/Kconfig: Rename CONFIG_LM32 -> CONFIG_LM32_PERIPHERALS
,
Alex Bennée
,
05:29
Re: [PATCH 02/10] hw/lm32/Kconfig: Introduce CONFIG_LM32_EVR for lm32-evr/uclinux boards
,
Alex Bennée
,
05:29
Re: [PATCH 01/10] hw/sh4/Kconfig: Rename CONFIG_SH4 -> CONFIG_SH4_PERIPHERALS
,
Alex Bennée
,
05:25
[
Prev Period
]
[
Next Period
]
Mail converted by
MHonArc