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[PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box hel
From: |
frank . chang |
Subject: |
[PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function |
Date: |
Fri, 26 Feb 2021 11:18:00 +0800 |
From: Frank Chang <frank.chang@sifive.com>
* Add fp16 nan-box check generator function, if a 16-bit input is not
properly nanboxed, then the input is replaced with the default qnan.
* Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
generate the NaN-boxed floating-point values based on SEW setting.
* Apply nanbox helper in opfvf_trans().
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 35 ++++++++++++++++++++++++-
target/riscv/translate.c | 10 +++++++
2 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 18a1c409fcf..ccfa93cf2f8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2100,6 +2100,33 @@ GEN_OPIVI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx)
/*
*** Vector Float Point Arithmetic Instructions
*/
+
+/*
+ * As RVF-only cpus always have values NaN-boxed to 64-bits,
+ * RVF and RVD can be treated equally.
+ * We don't have to deal with the cases of: SEW > FLEN.
+ *
+ * If SEW < FLEN, check whether input fp register is a valid
+ * NaN-boxed value, in which case the least-significant SEW bits
+ * of the f regsiter are used, else the canonical NaN value is used.
+ */
+static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)
+{
+ switch (s->sew) {
+ case 1:
+ gen_check_nanbox_h(out, in);
+ break;
+ case 2:
+ gen_check_nanbox_s(out, in);
+ break;
+ case 3:
+ tcg_gen_mov_i64(out, in);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
/* Vector Single-Width Floating-Point Add/Subtract Instructions */
/*
@@ -2152,6 +2179,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1,
uint32_t vs2,
{
TCGv_ptr dest, src2, mask;
TCGv_i32 desc;
+ TCGv_i64 t1;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
@@ -2165,12 +2193,17 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1,
uint32_t vs2,
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc);
+ /* NaN-box f[rs1] */
+ t1 = tcg_temp_new_i64();
+ do_nanbox(s, t1, cpu_fpr[rs1]);
+
+ fn(dest, mask, t1, src2, cpu_env, desc);
tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2);
tcg_temp_free_i32(desc);
+ tcg_temp_free_i64(t1);
mark_vs_dirty(s);
gen_set_label(over);
return true;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 75ed94c802b..d9a794d71e8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -123,6 +123,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
*
* Here, the result is always nan-boxed, even the canonical nan.
*/
+static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
+{
+ TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull);
+ TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull);
+
+ tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
+ tcg_temp_free_i64(t_max);
+ tcg_temp_free_i64(t_nan);
+}
+
static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
{
TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull);
--
2.17.1
- [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status, (continued)
- [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/02/25
- [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/02/25
- [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/02/25
- [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/02/25
- [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/02/25
- [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/02/25
- [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/02/25
- [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/02/25
- [PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2021/02/25
- [PATCH v7 14/75] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/02/25
- [PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function,
frank . chang <=
- [PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions, frank . chang, 2021/02/25
- [PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2021/02/25
- [PATCH v7 19/75] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2021/02/25
- [PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2021/02/25
- [PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2021/02/25
- [PATCH v7 22/75] target/riscv: rvv-1.0: amo operations, frank . chang, 2021/02/25
- [PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2021/02/25
- [PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2021/02/25
- [PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/02/25
- [PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2021/02/25