@@ -622,9 +632,15 @@ static void raise_mmu_exception(CPURISCVState *env,
target_ulong address,
CPUState *cs = env_cpu(env);
int page_fault_exceptions;
if (first_stage) {
- page_fault_exceptions =
- get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
- !pmp_violation;
+ if (riscv_cpu_is_32bit(env)) {
+ page_fault_exceptions =
+ get_field(env->satp, SATP32_MODE) != VM_1_10_MBARE &&
+ !pmp_violation;
+ } else {
+ page_fault_exceptions =
+ get_field(env->satp, SATP64_MODE) != VM_1_10_MBARE &&
+ !pmp_violation;
+ }
} else {
if (riscv_cpu_is_32bit(env)) {
page_fault_exceptions =
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6052b2d6e9..b0ebaa029e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -930,16 +930,31 @@ static int write_satp(CPURISCVState *env, int csrno,
target_ulong val)
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
return 0;
}
- if (validate_vm(env, get_field(val, SATP_MODE)) &&
- ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
- {
- if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -RISCV_EXCP_ILLEGAL_INST;
- } else {
- if ((val ^ env->satp) & SATP_ASID) {
- tlb_flush(env_cpu(env));
+ if (riscv_cpu_is_32bit(env)) {
+ if (validate_vm(env, get_field(val, SATP32_MODE)) &&
+ ((val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN)))
+ {
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ } else {
+ if ((val ^ env->satp) & SATP32_ASID) {
+ tlb_flush(env_cpu(env));
+ }
+ env->satp = val;
+ }
+ }