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Re: [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build
From: |
Richard Henderson |
Subject: |
Re: [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build |
Date: |
Tue, 6 Apr 2021 07:57:10 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 |
On 4/2/21 1:03 PM, Alistair Francis wrote:
Signed-off-by: Alistair Francis<alistair.francis@wdc.com>
---
target/riscv/insn16-32.decode | 24 ++++++++++++++++++++++++
target/riscv/insn16-64.decode | 31 +++++++++++++++++++++++++++++++
target/riscv/translate.c | 18 +++++++++++++++++-
target/riscv/meson.build | 7 +++++--
4 files changed, 77 insertions(+), 3 deletions(-)
Having these split out from the main decode file was a cool trick when we were
sure that we never needed to support both. Now, I think it would be better to
merge the patterns back in to the main insn16.decode file.
You'd begin by adding a REQUIRE_64BIT(ctx) macro, much like the other REQUIRE
macros in translate.c, using the translate-local is_32bit() function as
discussed earlier.
You add this to all of the trans_* functions that are currently #ifdef
TARGET_RISCV64, and merge the insn32-64.decode bits in first.
There may well be an issue of missing helper functions, particularly when it
comes to RVF/RVD/RVV. There's a suggestion that I made for Claudio for i386
that may help here:
https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg08595.html
where you add stubs that allow the gen_helper_foo() function to be declared,
insist that it be optimized away, and reduce to an abort with -O0.
Only after insn32.decode is complete, do insn16.decode. That's because many of
the insns here will need the REQUIRE_64BIT in place for correctness.
E.g.
{
ld 011 ... ... .. ... 00 @cl_d
flw 011 ... ... .. ... 00 @cl_w
}
Since ld already has REQUIRE_64BIT, for is_32bit it returns false, and we fall
into the flw code.
There will be one extra helper required, when the 64-bit RVC insn has a set of
illegal operands:
static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
{
REQUIRE_64BIT(ctx);
return trans_illegal(ctx, a);
}
for use with quadrant 1:
{
c64_illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
addiw 001 . ..... ..... 01 @ci
jal 001 ........... 01 @cj rd=1 # C.JAL
}
and quadrant 2:
{
c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
ld 011 . ..... ..... 10 @c_ldsp
flw 011 . ..... ..... 10 @c_lwsp
}
r~
- Re: [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro, (continued)