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qemu-riscv (date)
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Last Modified: Sat Jul 31 2021 16:54:08 -0400
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July 31, 2021
[PATCH] hw/char: Add config for shakti uart
,
Vijai Kumar K
,
16:54
July 30, 2021
Re: [PATCH for-6.2 09/43] target/riscv: Implement do_unaligned_access for user-only
,
Alistair Francis
,
02:13
July 28, 2021
[PATCH for-6.2 09/43] target/riscv: Implement do_unaligned_access for user-only
,
Richard Henderson
,
20:47
July 24, 2021
[PATCH v2 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine
,
Anup Patel
,
08:24
[PATCH v2 3/4] hw/riscv: virt: Re-factor FDT generation
,
Anup Patel
,
08:24
[PATCH v2 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
,
Anup Patel
,
08:24
[PATCH v2 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources
,
Anup Patel
,
08:24
[PATCH v2 0/4] QEMU RISC-V ACLINT Support
,
Anup Patel
,
08:24
July 23, 2021
Re: [PATCH v2 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
,
Alistair Francis
,
02:49
Re: [PATCH 14/17] target/riscv: Tidy trans_rvh.c.inc
,
Alistair Francis
,
01:03
Re: [PATCH 09/17] target/riscv: Reorg csr instructions
,
Alistair Francis
,
01:01
July 22, 2021
Re: [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
,
Anup Patel
,
23:37
July 19, 2021
Re:[PATCH 02/17] target/riscv: Introduce gpr_src, gpr_dst
,
LIU Zhiwei
,
23:41
July 17, 2021
Re: [PATCH 00/17] target/riscv: Use tcg_constant_*
,
Richard Henderson
,
11:41
Re: [PATCH 00/17] target/riscv: Use tcg_constant_*
,
LIU Zhiwei
,
00:00
July 15, 2021
Re: [PATCH 00/17] target/riscv: Use tcg_constant_*
,
Richard Henderson
,
12:15
Re: [PATCH v2 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
,
LIU Zhiwei
,
07:34
Re: [PATCH 00/17] target/riscv: Use tcg_constant_*
,
LIU Zhiwei
,
07:22
Re: [PATCH v2 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
,
Bin Meng
,
04:21
Re: [PATCH v2 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Bin Meng
,
04:21
Re: [PATCH v2 3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Bin Meng
,
04:21
Re: [PATCH v2 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
,
Bin Meng
,
04:21
Re: [PATCH v2 1/5] target/riscv: Expose interrupt pending bits as GPIO lines
,
Bin Meng
,
04:21
Re: [PATCH v2 1/1] hw/riscv/boot: Check the error of fdt_pack()
,
Alistair Francis
,
02:58
Re: [PATCH v1 1/1] hw/riscv/boot: Check the error of fdt_pack()
,
Alistair Francis
,
02:58
Re: [PATCH 17/17] target/riscv: Remove gen_get_gpr
,
Alistair Francis
,
01:09
Re: [PATCH 16/17] target/riscv: Use gpr_{src,dst} for RVV
,
Alistair Francis
,
01:05
Re: [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu
,
Alistair Francis
,
01:02
Re: [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD
,
Alistair Francis
,
01:01
Re: [PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF
,
Alistair Francis
,
00:59
Re: [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB
,
Alistair Francis
,
00:53
Re: [PATCH 10/17] target/riscv: Use gpr_{src,dst} for RVA
,
Alistair Francis
,
00:51
Re: [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations
,
Alistair Francis
,
00:49
July 14, 2021
[PATCH v2 1/1] hw/riscv/boot: Check the error of fdt_pack()
,
Alistair Francis
,
19:01
Re: [PATCH v1 1/1] hw/riscv/boot: Check the error of fdt_pack()
,
Peter Maydell
,
04:46
Re: [PATCH v1 1/1] hw/riscv/boot: Check the error of fdt_pack()
,
Bin Meng
,
03:32
[PATCH v2 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
,
Alistair Francis
,
03:25
[PATCH v2 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Alistair Francis
,
03:25
[PATCH v2 3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Alistair Francis
,
03:25
[PATCH v2 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
,
Alistair Francis
,
03:24
[PATCH v2 1/5] target/riscv: Expose interrupt pending bits as GPIO lines
,
Alistair Francis
,
03:24
[PATCH v1 1/1] hw/riscv/boot: Check the error of fdt_pack()
,
Alistair Francis
,
03:22
Re: [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
,
Alistair Francis
,
02:11
July 13, 2021
Re: [RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode
,
Frank Chang
,
03:16
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
02:57
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
02:54
Re: [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Anup Patel
,
01:08
Re: [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Anup Patel
,
00:31
Re: [PATCH 07/17] target/riscv: Use gpr_{src, dst} for integer load/store
,
Alistair Francis
,
00:18
Re: [PATCH 06/17] target/riscv: Use gpr_src in branches
,
Alistair Francis
,
00:15
Re: [PATCH 05/17] target/riscv: Use gpr_{src, dst} and tcg_constant_tl in gen_grevi
,
Alistair Francis
,
00:13
Re: [PATCH 04/17] target/riscv: Use gpr_{src, dst} in word division operations
,
Alistair Francis
,
00:11
Re: [PATCH 03/17] target/riscv: Use gpr_{src, dst} in shift operations
,
Alistair Francis
,
00:10
Re: [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
,
Anup Patel
,
00:06
July 12, 2021
Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
,
Bin Meng
,
19:05
Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
,
Anup Patel
,
11:03
Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
,
Bin Meng
,
09:11
Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
,
Anup Patel
,
06:54
Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
,
Bin Meng
,
02:15
Re: [PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation
,
Anup Patel
,
01:41
Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
,
Anup Patel
,
01:39
Re: [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
,
Anup Patel
,
01:33
Re: [PATCH v2 3/3] hw/riscv: opentitan: Add the flash alias
,
Alistair Francis
,
01:14
Re: [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
,
Anup Patel
,
01:00
Re: [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
,
Alistair Francis
,
00:49
July 10, 2021
Re: [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode
,
Frank Chang
,
11:05
Re: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode
,
Frank Chang
,
11:00
Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines
,
Bin Meng
,
10:41
July 09, 2021
Re: [PATCH 01/17] target/riscv: Use tcg_constant_*
,
Philippe Mathieu-Daudé
,
12:20
Re: [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
,
Richard Henderson
,
11:44
Re: [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Richard Henderson
,
11:41
Re: [PATCH v1 3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Richard Henderson
,
11:39
Re: [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
,
Richard Henderson
,
11:36
Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines
,
Richard Henderson
,
11:21
Re: [PATCH v2 3/3] hw/riscv: opentitan: Add the flash alias
,
Bin Meng
,
08:21
Re: [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
,
Philippe Mathieu-Daudé
,
03:26
Re: [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Philippe Mathieu-Daudé
,
03:26
Re: [PATCH v1 3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Philippe Mathieu-Daudé
,
03:26
Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines
,
Philippe Mathieu-Daudé
,
03:25
Re: [PATCH 02/17] target/riscv: Introduce gpr_src, gpr_dst
,
Alistair Francis
,
01:45
Re: [PATCH 01/17] target/riscv: Use tcg_constant_*
,
Alistair Francis
,
01:41
Re: [PATCH] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
,
Alistair Francis
,
00:42
[PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD
,
Richard Henderson
,
00:27
[PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu
,
Richard Henderson
,
00:27
[PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations
,
Richard Henderson
,
00:27
[PATCH 10/17] target/riscv: Use gpr_{src,dst} for RVA
,
Richard Henderson
,
00:26
[PATCH 09/17] target/riscv: Reorg csr instructions
,
Richard Henderson
,
00:26
[PATCH 00/17] target/riscv: Use tcg_constant_*
,
Richard Henderson
,
00:26
[PATCH 04/17] target/riscv: Use gpr_{src, dst} in word division operations
,
Richard Henderson
,
00:26
[PATCH 03/17] target/riscv: Use gpr_{src,dst} in shift operations
,
Richard Henderson
,
00:26
[PATCH 14/17] target/riscv: Tidy trans_rvh.c.inc
,
Richard Henderson
,
00:26
[PATCH 16/17] target/riscv: Use gpr_{src,dst} for RVV
,
Richard Henderson
,
00:26
[PATCH 17/17] target/riscv: Remove gen_get_gpr
,
Richard Henderson
,
00:26
[PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF
,
Richard Henderson
,
00:26
[PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB
,
Richard Henderson
,
00:26
[PATCH 07/17] target/riscv: Use gpr_{src,dst} for integer load/store
,
Richard Henderson
,
00:26
[PATCH 06/17] target/riscv: Use gpr_src in branches
,
Richard Henderson
,
00:26
[PATCH 01/17] target/riscv: Use tcg_constant_*
,
Richard Henderson
,
00:26
[PATCH 02/17] target/riscv: Introduce gpr_src, gpr_dst
,
Richard Henderson
,
00:26
[PATCH 05/17] target/riscv: Use gpr_{src, dst} and tcg_constant_tl in gen_grevi
,
Richard Henderson
,
00:26
July 08, 2021
Re: [PATCH] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
,
Alistair Francis
,
23:52
Re: [PATCH] hw/riscv: sifive_u: Correct the CLINT timebase frequency
,
Alistair Francis
,
23:51
Re: [PATCH] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
,
Alistair Francis
,
23:50
[PATCH v2 3/3] hw/riscv: opentitan: Add the flash alias
,
Alistair Francis
,
23:39
[PATCH v2 2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
,
Alistair Francis
,
23:38
[PATCH v2 1/3] char: ibex_uart: Update the register layout
,
Alistair Francis
,
23:38
[PATCH v2 0/3] Updates to the OpenTitan machine
,
Alistair Francis
,
23:38
[PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
,
Alistair Francis
,
23:31
[PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Alistair Francis
,
23:31
[PATCH v1 3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
,
Alistair Francis
,
23:31
[PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
,
Alistair Francis
,
23:31
[PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines
,
Alistair Francis
,
23:31
[PATCH] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
,
Bin Meng
,
10:33
Re: [PATCH] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
,
Alistair Francis
,
00:50
Re: [PATCH] hw/riscv: sifive_u: Correct the CLINT timebase frequency
,
Alistair Francis
,
00:48
Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg
,
Alistair Francis
,
00:46
July 07, 2021
Re: [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V
,
Laurent Vivier
,
15:15
[PATCH v2 1/5] meson: Introduce target-specific Kconfig
,
Alex Bennée
,
09:17
July 06, 2021
[PATCH v2 32/36] linux-user/riscv: Add vdso and use it for sigreturn
,
Richard Henderson
,
19:50
Re: [PATCH v1 1/5] meson: Introduce target-specific Kconfig
,
Alex Bennée
,
09:55
Re: [PATCH v1 1/5] meson: Introduce target-specific Kconfig
,
Philippe Mathieu-Daudé
,
09:40
Re: [PATCH v1 1/5] meson: Introduce target-specific Kconfig
,
Thomas Huth
,
09:10
Re: [PATCH v1 1/5] meson: Introduce target-specific Kconfig
,
Philippe Mathieu-Daudé
,
08:48
Re: [PATCH v1 1/5] meson: Introduce target-specific Kconfig
,
Thomas Huth
,
06:52
[PATCH] hw/riscv: sifive_u: Correct the CLINT timebase frequency
,
Bin Meng
,
06:25
[PATCH] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
,
Bin Meng
,
05:50
Re: [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V
,
Bin Meng
,
01:51
Re: [PATCH v1 3/3] hw/riscv: opentitan: Add the flash alias
,
Alistair Francis
,
00:50
Re: [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V
,
Richard Henderson
,
00:42
July 05, 2021
[PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V
,
Kito Cheng
,
23:50
Re: [PATCH v2] linux-user/elfload: Implement ELF_HWCAP for RISC-V
,
Richard Henderson
,
23:29
[PATCH v2] linux-user/elfload: Implement ELF_HWCAP for RISC-V
,
Kito Cheng
,
02:43
Re: [PATCH v1 2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
,
Bin Meng
,
02:17
Re: [PATCH v1 1/3] char: ibex_uart: Update the register layout
,
Bin Meng
,
02:17
Re: [PATCH v1 3/3] hw/riscv: opentitan: Add the flash alias
,
Bin Meng
,
02:16
Re: [PATCH 2/2] docs/system: riscv: Add documentation for virt machine
,
Alistair Francis
,
01:36
July 02, 2021
Re: [PATCH 2/2] docs/system: riscv: Add documentation for virt machine
,
Alistair Francis
,
03:24
Re: [PATCH v2] target/riscv: csr: Remove redundant check in fp csr read/write routines
,
Alistair Francis
,
03:22
Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
,
Alistair Francis
,
03:17
Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
,
LIU Zhiwei
,
02:11
Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
,
Alistair Francis
,
01:39
[PATCH v1 3/3] hw/riscv: opentitan: Add the flash alias
,
Alistair Francis
,
01:20
[PATCH v1 2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
,
Alistair Francis
,
01:20
[PATCH v1 1/3] char: ibex_uart: Update the register layout
,
Alistair Francis
,
01:19
[PATCH v1 0/3] Updates to the OpenTitan machine
,
Alistair Francis
,
01:19
July 01, 2021
Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
,
LIU Zhiwei
,
05:39
Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
,
Frank Chang
,
04:45
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