Re: [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V

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Re: [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V

From:	Richard Henderson
Subject:	Re: [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
Date:	Fri, 9 Jul 2021 08:43:55 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0

On 7/8/21 8:31 PM, Alistair Francis wrote:

@@ -48,5 +48,7 @@ struct IbexTimerState {
      uint32_t timebase_freq;

qemu_irq irq;

+
+    qemu_irq m_timer_irqs;


The plural here is a bit misleading.  Otherwise,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

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[PATCH v1 3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines, (continued)
- [PATCH v1 3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Alistair Francis, 2021/07/08
  - Re: [PATCH v1 3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Philippe Mathieu-Daudé, 2021/07/09
  - Re: [PATCH v1 3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Richard Henderson, 2021/07/09
- [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Alistair Francis, 2021/07/08
  - Re: [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Philippe Mathieu-Daudé, 2021/07/09
  - Re: [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Richard Henderson, 2021/07/09
  - Re: [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Anup Patel, 2021/07/13
  - Re: [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Anup Patel, 2021/07/13
- [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines, Alistair Francis, 2021/07/08
  - Re: [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines, Philippe Mathieu-Daudé, 2021/07/09
  - Re: [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines, Richard Henderson <=
- Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines, Philippe Mathieu-Daudé, 2021/07/09
- Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines, Richard Henderson, 2021/07/09
- Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines, Bin Meng, 2021/07/10

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