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qemu-riscv (date)
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Last Modified: Sun Oct 31 2021 19:35:56 -0400
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October 31, 2021
Re: [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts
,
Alistair Francis
,
19:35
Re: [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions
,
Richard Henderson
,
00:03
October 30, 2021
Re: [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions
,
Richard Henderson
,
23:49
Re: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions
,
Richard Henderson
,
23:44
Re: [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store
,
Richard Henderson
,
23:41
Re: [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles
,
Richard Henderson
,
19:52
Re: [PATCH v4 03/17] target/riscv: additional macros to check instruction support
,
Richard Henderson
,
19:50
[PATCH v2 6/7] target/riscv: cpu: Enable native debug feature on virt and sifive_u CPUs
,
Bin Meng
,
09:55
[PATCH v2 5/7] target/riscv: csr: Hook debug CSR read/write
,
Bin Meng
,
09:55
[PATCH v2 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
,
Bin Meng
,
09:55
[PATCH v2 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
,
Bin Meng
,
09:55
[PATCH v2 2/7] target/riscv: machine: Add debug state description
,
Bin Meng
,
09:55
[PATCH v2 4/7] target/riscv: cpu: Add a config option for native debug
,
Bin Meng
,
09:55
[PATCH v2 3/7] target/riscv: debug: Implement debug related TCGCPUOps
,
Bin Meng
,
09:55
[PATCH v2 1/7] target/riscv: Add initial support for native debug
,
Bin Meng
,
09:55
October 29, 2021
[PATCH] target/riscv: machine: Sort the .subsections
,
Bin Meng
,
23:06
Re: [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
,
Richard Henderson
,
15:46
Re: [PATCH 1/5] target/riscv: Add initial support for native debug
,
Richard Henderson
,
15:41
Re: [PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps
,
Richard Henderson
,
15:36
Re: [PATCH 3/5] target/riscv: Add a config option for native debug
,
Richard Henderson
,
15:34
Re: [PATCH 5/5] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
,
Richard Henderson
,
15:33
[PATCH 5/5] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
,
Bin Meng
,
11:26
[PATCH 4/5] target/riscv: csr: Hook debug CSR read/write
,
Bin Meng
,
11:25
[PATCH 3/5] target/riscv: Add a config option for native debug
,
Bin Meng
,
11:25
[PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps
,
Bin Meng
,
11:25
[PATCH 1/5] target/riscv: Add initial support for native debug
,
Bin Meng
,
11:25
[PATCH 0/5] target/riscv: Initial support for native debug feature via M-mode CSRs
,
Bin Meng
,
11:25
[PATCH v9 76/76] target/riscv: rvv-1.0: update opivv_vadc_check() comment
,
frank . chang
,
05:04
[PATCH v9 75/76] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
,
frank . chang
,
05:04
[PATCH v9 74/76] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
,
frank . chang
,
05:04
[PATCH v9 73/76] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
,
frank . chang
,
05:04
[PATCH v9 72/76] target/riscv: rvv-1.0: add vsetivli instruction
,
frank . chang
,
05:04
[PATCH v9 71/76] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
,
frank . chang
,
05:04
[PATCH v9 70/76] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
,
frank . chang
,
05:04
[PATCH v9 68/76] target/riscv: gdb: support vector registers for rv64 & rv32
,
frank . chang
,
05:04
[PATCH v9 69/76] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
,
frank . chang
,
05:04
[PATCH v9 67/76] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
,
frank . chang
,
05:03
[PATCH v9 66/76] target/riscv: rvv-1.0: implement vstart CSR
,
frank . chang
,
05:03
[PATCH v9 65/76] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
,
frank . chang
,
05:03
[PATCH v9 64/76] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
,
frank . chang
,
05:03
[PATCH v9 60/76] target/riscv: introduce floating-point rounding mode enum
,
frank . chang
,
05:03
[PATCH v9 63/76] target/riscv: add "set round to odd" rounding mode helper function
,
frank . chang
,
05:03
[PATCH v9 62/76] target/riscv: rvv-1.0: widening floating-point/integer type-convert
,
frank . chang
,
05:03
[PATCH v9 61/76] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
,
frank . chang
,
05:03
[PATCH v9 59/76] target/riscv: rvv-1.0: floating-point min/max instructions
,
frank . chang
,
05:03
[PATCH v9 58/76] target/riscv: rvv-1.0: remove integer extract instruction
,
frank . chang
,
05:03
[PATCH v9 57/76] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
,
frank . chang
,
05:03
[PATCH v9 56/76] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
,
frank . chang
,
05:03
[PATCH v9 55/76] target/riscv: rvv-1.0: single-width scaling shift instructions
,
frank . chang
,
05:03
[PATCH v9 54/76] target/riscv: rvv-1.0: widening floating-point reduction instructions
,
frank . chang
,
05:03
[PATCH v9 53/76] target/riscv: rvv-1.0: single-width floating-point reduction
,
frank . chang
,
05:03
[PATCH v9 52/76] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
,
frank . chang
,
05:03
[PATCH v9 51/76] target/riscv: rvv-1.0: floating-point slide instructions
,
frank . chang
,
05:02
[PATCH v9 50/76] target/riscv: rvv-1.0: slide instructions
,
frank . chang
,
05:02
[PATCH v9 49/76] target/riscv: rvv-1.0: mask-register logical instructions
,
frank . chang
,
05:02
[PATCH v9 48/76] target/riscv: rvv-1.0: floating-point compare instructions
,
frank . chang
,
05:02
[PATCH v9 47/76] target/riscv: rvv-1.0: integer comparison instructions
,
frank . chang
,
05:02
[PATCH v9 46/76] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
,
frank . chang
,
05:02
[PATCH v9 45/76] target/riscv: rvv-1.0: widening integer multiply-add instructions
,
frank . chang
,
05:02
[PATCH v9 44/76] target/riscv: rvv-1.0: narrowing integer right shift instructions
,
frank . chang
,
05:02
[PATCH v9 43/76] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
,
frank . chang
,
05:02
[PATCH v9 42/76] target/riscv: rvv-1.0: single-width bit shift instructions
,
frank . chang
,
05:02
[PATCH v9 41/76] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
,
frank . chang
,
05:02
[PATCH v9 39/76] target/riscv: rvv-1.0: whole register move instructions
,
frank . chang
,
05:02
[PATCH v9 40/76] target/riscv: rvv-1.0: integer extension instructions
,
frank . chang
,
05:02
[PATCH v9 37/76] target/riscv: rvv-1.0: floating-point move instruction
,
frank . chang
,
05:02
[PATCH v9 36/76] target/riscv: rvv-1.0: integer scalar move instructions
,
frank . chang
,
05:02
[PATCH v9 31/76] target/riscv: rvv-1.0: set-X-first mask bit instructions
,
frank . chang
,
05:02
[PATCH v9 30/76] target/riscv: rvv-1.0: find-first-set mask bit instruction
,
frank . chang
,
05:02
[PATCH v9 24/76] target/riscv: rvv-1.0: load/store whole register instructions
,
frank . chang
,
05:02
[PATCH v9 27/76] target/riscv: rvv-1.0: floating-point square-root instruction
,
frank . chang
,
05:02
[PATCH v9 35/76] target/riscv: rvv-1.0: register gather instructions
,
frank . chang
,
05:02
[PATCH v9 38/76] target/riscv: rvv-1.0: floating-point scalar move instructions
,
frank . chang
,
05:02
[PATCH v9 33/76] target/riscv: rvv-1.0: element index instruction
,
frank . chang
,
05:02
[PATCH v9 34/76] target/riscv: rvv-1.0: allow load element with sign-extended
,
frank . chang
,
05:02
[PATCH v9 32/76] target/riscv: rvv-1.0: iota instruction
,
frank . chang
,
05:01
[PATCH v9 28/76] target/riscv: rvv-1.0: floating-point classify instructions
,
frank . chang
,
05:01
[PATCH v9 23/76] target/riscv: rvv-1.0: fault-only-first unit stride load
,
frank . chang
,
05:01
[PATCH v9 29/76] target/riscv: rvv-1.0: count population in mask instruction
,
frank . chang
,
05:01
[PATCH v9 21/76] target/riscv: rvv-1.0: index load and store instructions
,
frank . chang
,
05:01
[PATCH v9 26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
,
frank . chang
,
05:01
[PATCH v9 25/76] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
,
frank . chang
,
05:01
[PATCH v9 22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
,
frank . chang
,
05:01
[PATCH v9 20/76] target/riscv: rvv-1.0: stride load and store instructions
,
frank . chang
,
05:00
[PATCH v9 19/76] target/riscv: rvv-1.0: configure instructions
,
frank . chang
,
05:00
[PATCH v9 18/76] target/riscv: rvv-1.0: remove amo operations instructions
,
frank . chang
,
05:00
[PATCH v9 17/76] target/riscv: rvv:1.0: add translation-time nan-box helper function
,
frank . chang
,
05:00
[PATCH v9 16/76] target/riscv: introduce more imm value modes in translator functions
,
frank . chang
,
05:00
[PATCH v9 15/76] target/riscv: rvv-1.0: update check functions
,
frank . chang
,
05:00
[PATCH v9 14/76] target/riscv: rvv-1.0: add VMA and VTA
,
frank . chang
,
05:00
[PATCH v9 13/76] target/riscv: rvv-1.0: add fractional LMUL
,
frank . chang
,
05:00
[PATCH v9 12/76] target/riscv: rvv-1.0: remove MLEN calculations
,
frank . chang
,
05:00
[PATCH v9 11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
,
frank . chang
,
05:00
[PATCH v9 09/76] target/riscv: rvv-1.0: add vcsr register
,
frank . chang
,
05:00
[PATCH v9 10/76] target/riscv: rvv-1.0: add vlenb register
,
frank . chang
,
05:00
[PATCH v9 08/76] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
,
frank . chang
,
05:00
[PATCH v9 07/76] target/riscv: rvv-1.0: add translation-time vector context status
,
frank . chang
,
05:00
[PATCH v9 05/76] target/riscv: rvv-1.0: add sstatus VS field
,
frank . chang
,
04:59
[PATCH v9 06/76] target/riscv: rvv-1.0: introduce writable misa.v field
,
frank . chang
,
04:59
[PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
,
frank . chang
,
04:59
[PATCH v9 03/76] target/riscv: rvv-1.0: add mstatus VS field
,
frank . chang
,
04:59
[PATCH v9 02/76] target/riscv: Use FIELD_EX32() to extract wd field
,
frank . chang
,
04:59
[PATCH v9 01/76] target/riscv: drop vector 0.7.1 and add 1.0 support
,
frank . chang
,
04:59
[PATCH v9 00/76] support vector extension v1.0
,
frank . chang
,
04:59
October 27, 2021
Re: [PATCH v2 0/2] mconfigptr support
,
Rahul Pathak
,
22:34
Re: [PATCH v2 1/2] target/riscv: Add priv spec 1.12.0 version check
,
Rahul Pathak
,
22:33
Re: [PATCH v2 2/2] target/riscv: csr: Implement mconfigptr CSR
,
Rahul Pathak
,
22:32
October 26, 2021
Re: [PATCH v2 2/2] target/riscv: remove force HS exception
,
Alistair Francis
,
23:25
Re: [PATCH v2 1/2] target/riscv: fix VS interrupts forwarding to HS
,
Alistair Francis
,
23:24
Re: [PATCH v2 0/2] mconfigptr support
,
Alistair Francis
,
22:45
Re: [PATCH v2 2/2] target/riscv: csr: Implement mconfigptr CSR
,
Alistair Francis
,
22:43
Re: [PATCH v2 1/2] target/riscv: Add priv spec 1.12.0 version check
,
Alistair Francis
,
22:38
[PATCH v2 2/2] target/riscv: remove force HS exception
,
Jose Martins
,
10:53
[PATCH v2 1/2] target/riscv: fix VS interrupts forwarding to HS
,
Jose Martins
,
10:53
Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS
,
Alistair Francis
,
02:58
Re: [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
,
Alistair Francis
,
02:56
Re: [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction
,
Alistair Francis
,
02:52
Re: [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
,
Alistair Francis
,
02:50
Re: [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment
,
Alistair Francis
,
02:50
[PATCH v4 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine
,
Anup Patel
,
02:44
[PATCH v4 22/22] docs/system: riscv: Document AIA options for virt machine
,
Anup Patel
,
02:44
[PATCH v4 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
,
Anup Patel
,
02:44
[PATCH v4 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
02:44
[PATCH v4 18/22] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
02:44
[PATCH v4 17/22] target/riscv: Allow users to force enable AIA CSRs in HART
,
Anup Patel
,
02:44
[PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available
,
Anup Patel
,
02:44
[PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs
,
Anup Patel
,
02:44
[PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs
,
Anup Patel
,
02:43
[PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Anup Patel
,
02:43
[PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs
,
Anup Patel
,
02:43
[PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Anup Patel
,
02:43
[PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Anup Patel
,
02:43
[PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
02:43
[PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Anup Patel
,
02:43
[PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
,
Anup Patel
,
02:43
[PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts
,
Anup Patel
,
02:43
[PATCH v4 07/22] target/riscv: Add defines for AIA CSRs
,
Anup Patel
,
02:43
[PATCH v4 06/22] target/riscv: Add AIA cpu feature
,
Anup Patel
,
02:43
[PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs
,
Anup Patel
,
02:43
[PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation
,
Anup Patel
,
02:43
[PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
,
Anup Patel
,
02:43
[PATCH v4 00/22] QEMU RISC-V AIA support
,
Anup Patel
,
02:43
Re: [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
,
Alistair Francis
,
02:33
Re: [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function
,
Alistair Francis
,
02:31
Re: [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert
,
Alistair Francis
,
02:30
Re: [PATCH v3 00/22] QEMU RISC-V AIA support
,
Anup Patel
,
01:03
October 25, 2021
Re: [PATCH] hw/riscv: opentitan: Fixup the PLIC context addresses
,
Alistair Francis
,
18:34
Re: [PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs
,
Alistair Francis
,
18:32
Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations
,
Richard Henderson
,
16:16
Re: [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO
,
Richard Henderson
,
16:09
[ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
15:56
[ PATCH v3 09/10] target/riscv: Add few cache related PMU events
,
Atish Patra
,
15:56
[ PATCH v3 08/10] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
15:56
[ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents
,
Atish Patra
,
15:56
[ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
15:56
[ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR
,
Atish Patra
,
15:56
[ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable
,
Atish Patra
,
15:56
[ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function
,
Atish Patra
,
15:56
[ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu
,
Atish Patra
,
15:56
[ PATCH v3 00/10] Improve PMU support
,
Atish Patra
,
15:56
[ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for
,
Atish Patra
,
15:56
Re: [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers
,
Richard Henderson
,
15:10
Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers
,
Richard Henderson
,
15:08
Re: [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
,
Richard Henderson
,
14:47
[PATCH v17 8/8] target/riscv: Allow experimental J-ext to be turned on
,
Alexey Baturo
,
13:36
[PATCH v17 6/8] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Alexey Baturo
,
13:36
[PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs
,
Alexey Baturo
,
13:36
[PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
,
Alexey Baturo
,
13:36
[PATCH v17 2/8] target/riscv: Add CSR defines for RISC-V PM extension
,
Alexey Baturo
,
13:36
[PATCH v17 4/8] target/riscv: Add J extension state description
,
Alexey Baturo
,
13:36
[PATCH v17 0/8] RISC-V Pointer Masking implementation
,
Alexey Baturo
,
13:36
[PATCH v17 1/8] target/riscv: Add J-extension into RISC-V
,
Alexey Baturo
,
13:36
[PATCH v17 7/8] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension
,
Alexey Baturo
,
13:36
Re: [PATCH v4 07/17] target/riscv: moving some insns close to similar insns
,
Philippe Mathieu-Daudé
,
11:56
Re: [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers
,
Philippe Mathieu-Daudé
,
11:55
Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers
,
Philippe Mathieu-Daudé
,
11:51
Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations
,
Philippe Mathieu-Daudé
,
11:47
Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
,
Richard Henderson
,
10:58
[PATCH v2 2/2] target/riscv: csr: Implement mconfigptr CSR
,
Rahul Pathak
,
08:44
[PATCH v2 1/2] target/riscv: Add priv spec 1.12.0 version check
,
Rahul Pathak
,
08:43
[PATCH v2 0/2] mconfigptr support
,
Rahul Pathak
,
08:43
[PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions
,
Frédéric Pétrot
,
08:29
[PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns
,
Frédéric Pétrot
,
08:29
[PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns
,
Frédéric Pétrot
,
08:29
[PATCH v4 16/17] target/riscv: modification of the trans_csrxx for 128-bit support
,
Frédéric Pétrot
,
08:29
[PATCH v4 14/17] target/riscv: adding high part of some csrs
,
Frédéric Pétrot
,
08:29
[PATCH v4 13/17] target/riscv: support for 128-bit M extension
,
Frédéric Pétrot
,
08:29
[PATCH v4 11/17] target/riscv: support for 128-bit shift instructions
,
Frédéric Pétrot
,
08:29
[PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions
,
Frédéric Pétrot
,
08:29
[PATCH v4 07/17] target/riscv: moving some insns close to similar insns
,
Frédéric Pétrot
,
08:28
[PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles
,
Frédéric Pétrot
,
08:28
[PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store
,
Frédéric Pétrot
,
08:28
[PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions
,
Frédéric Pétrot
,
08:28
[PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers
,
Frédéric Pétrot
,
08:28
[PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations
,
Frédéric Pétrot
,
08:28
[PATCH v4 03/17] target/riscv: additional macros to check instruction support
,
Frédéric Pétrot
,
08:28
[PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO
,
Frédéric Pétrot
,
08:28
[PATCH v4 00/17] Adding partial support for 128-bit riscv target
,
Frédéric Pétrot
,
08:28
[PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers
,
Frédéric Pétrot
,
08:28
Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS
,
Jose Martins
,
05:48
Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
,
LIU Zhiwei
,
05:24
Re: [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
,
Alistair Francis
,
02:43
Re: [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs
,
Alistair Francis
,
02:43
Re: [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
,
Alistair Francis
,
02:17
Re: [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point slide instructions
,
Alistair Francis
,
02:14
Re: [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
,
Alistair Francis
,
02:09
Re: [PATCH v16 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
,
Alistair Francis
,
01:54
Re: [PATCH v16 0/8] RISC-V Pointer Masking implementation
,
Alistair Francis
,
00:16
Re: [PATCH] hw/riscv: opentitan: Fixup the PLIC context addresses
,
Bin Meng
,
00:16
[PATCH] hw/riscv: opentitan: Fixup the PLIC context addresses
,
Alistair Francis
,
00:07
October 24, 2021
Re: [PATCH v16 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs
,
Alistair Francis
,
21:22
Re: [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions
,
Frédéric Pétrot
,
18:49
October 23, 2021
Re: [PATCH] tests/tcg: Fix some targets default cross compiler path
,
Philippe Mathieu-Daudé
,
14:07
Re: [PATCH] tests/tcg: Fix some targets default cross compiler path
,
Alex Bennée
,
13:47
[PATCH] tests/tcg: Fix some targets default cross compiler path
,
Philippe Mathieu-Daudé
,
12:43
[PATCH v3 22/22] docs/system: riscv: Document AIA options for virt machine
,
Anup Patel
,
04:48
[PATCH v3 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
,
Anup Patel
,
04:48
[PATCH v3 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
04:48
[PATCH v3 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine
,
Anup Patel
,
04:48
[PATCH v3 18/22] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
04:48
[PATCH v3 17/22] target/riscv: Allow users to force enable AIA CSRs in HART
,
Anup Patel
,
04:48
[PATCH v3 16/22] hw/riscv: virt: Use AIA INTC compatible string when available
,
Anup Patel
,
04:48
[PATCH v3 14/22] target/riscv: Implement AIA xiselect and xireg CSRs
,
Anup Patel
,
04:48
[PATCH v3 15/22] target/riscv: Implement AIA IMSIC interface CSRs
,
Anup Patel
,
04:48
[PATCH v3 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Anup Patel
,
04:48
[PATCH v3 05/22] target/riscv: Allow setting CPU feature from machine/device emulation
,
Anup Patel
,
04:48
[PATCH v3 12/22] target/riscv: Implement AIA interrupt filtering CSRs
,
Anup Patel
,
04:48
[PATCH v3 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Anup Patel
,
04:48
[PATCH v3 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Anup Patel
,
04:48
[PATCH v3 09/22] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
04:48
[PATCH v3 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Anup Patel
,
04:48
[PATCH v3 07/22] target/riscv: Add defines for AIA CSRs
,
Anup Patel
,
04:47
[PATCH v3 06/22] target/riscv: Add AIA cpu feature
,
Anup Patel
,
04:47
[PATCH v3 04/22] target/riscv: Improve delivery of guest external interrupts
,
Anup Patel
,
04:47
[PATCH v3 03/22] target/riscv: Implement hgeie and hgeip CSRs
,
Anup Patel
,
04:47
[PATCH v3 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
,
Anup Patel
,
04:47
[PATCH v3 00/22] QEMU RISC-V AIA support
,
Anup Patel
,
04:47
[PATCH v3 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
,
Anup Patel
,
04:47
October 22, 2021
[PATCH v16 4/8] [RISCV_PM] Add J extension state description
,
Alexey Baturo
,
14:19
[PATCH v16 8/8] [RISCV_PM] Allow experimental J-ext to be turned on
,
Alexey Baturo
,
14:19
[PATCH v16 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs
,
Alexey Baturo
,
14:19
[PATCH v16 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
,
Alexey Baturo
,
14:19
[PATCH v16 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension
,
Alexey Baturo
,
14:19
[PATCH v16 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
,
Alexey Baturo
,
14:19
[PATCH v16 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Alexey Baturo
,
14:19
[PATCH v16 1/8] [RISCV_PM] Add J-extension into RISC-V
,
Alexey Baturo
,
14:19
[PATCH v16 0/8] RISC-V Pointer Masking implementation
,
Alexey Baturo
,
14:19
Re: [RFC PATCH v1 2/2] Enable custom instruction suport for Andes A25 and AX25 CPU model
,
Richard Henderson
,
13:24
Re: [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()
,
Richard Henderson
,
12:00
Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
,
Richard Henderson
,
11:50
Re: [PATCH v2 5/5] hw/riscv: virt: Use the PLIC config helper function
,
Bin Meng
,
10:58
Re: [PATCH v2 4/5] hw/riscv: microchip_pfsoc: Use the PLIC config helper function
,
Bin Meng
,
10:58
Re: [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function
,
Bin Meng
,
10:58
Re: [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function
,
Bin Meng
,
09:54
Re: [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration
,
Bin Meng
,
09:45
Re: [RFC PATCH v1 2/2] Enable custom instruction suport for Andes A25 and AX25 CPU model
,
Alex Bennée
,
07:59
Re: [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration
,
Philippe Mathieu-Daudé
,
06:38
Re: [RFC PATCH v1 2/2] Enable custom instruction suport for Andes A25 and AX25 CPU model
,
Ruinland ChuanTzu Tsai
,
04:49
Re: [RFC PATCH v1 1/2] riscv: Add preliminary infra for custom instrcution handling
,
Ruinland ChuanTzu Tsai
,
04:42
Re: [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()
,
Ruinland ChuanTzu Tsai
,
04:41
Re: [RFC PATCH v5 3/3] riscv: Enable custom CSR support for Andes AX25 and A25 CPUs
,
Ruinland ChuanTzu Tsai
,
04:41
Re: [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()
,
Ruinland ChuanTzu Tsai
,
04:41
Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
,
LIU Zhiwei
,
04:26
Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers
,
Frédéric Pétrot
,
02:06
[PATCH v2 5/5] hw/riscv: virt: Use the PLIC config helper function
,
Alistair Francis
,
02:02
[PATCH v2 4/5] hw/riscv: microchip_pfsoc: Use the PLIC config helper function
,
Alistair Francis
,
02:02
[PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function
,
Alistair Francis
,
02:02
[PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function
,
Alistair Francis
,
02:02
[PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration
,
Alistair Francis
,
02:01
October 21, 2021
Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store
,
Frank Chang
,
23:25
Re: [RFC PATCH v5 3/3] riscv: Enable custom CSR support for Andes AX25 and A25 CPUs
,
Richard Henderson
,
21:12
Re: [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()
,
Richard Henderson
,
20:08
Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store
,
Richard Henderson
,
19:28
Re: [PATCH v15 0/8] RISC-V Pointer Masking implementation
,
Alistair Francis
,
18:57
Re: [RFC PATCH v5 0/3] riscv: Add preliminary custom CSR support
,
Alistair Francis
,
18:48
Re: [RFC PATCH v5 3/3] riscv: Enable custom CSR support for Andes AX25 and A25 CPUs
,
Alistair Francis
,
18:45
Re: [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()
,
Alistair Francis
,
18:43
Re: [RFC PATCH v5 1/3] riscv: Adding Andes A25 and AX25 cpu models
,
Alistair Francis
,
18:34
Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store
,
Alistair Francis
,
18:32
Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store
,
Alistair Francis
,
18:04
Re: [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function
,
Alistair Francis
,
17:59
Re: [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines
,
Alistair Francis
,
17:58
Re: [RFC PATCH v1 2/2] Enable custom instruction suport for Andes A25 and AX25 CPU model
,
Richard Henderson
,
15:18
Re: [PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation
,
Anup Patel
,
13:06
[PATCH v5 5/8] target/riscv: zfh: half-precision floating-point classify
,
frank . chang
,
12:30
[PATCH v5 7/8] target/riscv: zfh: implement zfhmin extension
,
frank . chang
,
12:30
[PATCH v5 8/8] target/riscv: zfh: add Zfhmin cpu property
,
frank . chang
,
12:30
[PATCH v5 6/8] target/riscv: zfh: add Zfh cpu property
,
frank . chang
,
12:30
[PATCH v5 4/8] target/riscv: zfh: half-precision floating-point compare
,
frank . chang
,
12:30
[PATCH v5 3/8] target/riscv: zfh: half-precision convert and move
,
frank . chang
,
12:30
[PATCH v5 2/8] target/riscv: zfh: half-precision computational
,
frank . chang
,
12:30
[PATCH v5 1/8] target/riscv: zfh: half-precision load and store
,
frank . chang
,
12:30
[PATCH v5 0/8] target/riscv: support Zfh, Zfhmin extension v0.1
,
frank . chang
,
12:30
Re: [PATCH v3 04/21] target/riscv: additional macros to check instruction support
,
Frédéric Pétrot
,
12:22
Re: [RFC PATCH v1 1/2] riscv: Add preliminary infra for custom instrcution handling
,
Richard Henderson
,
12:11
[PATCH v5 2/2] target/riscv: change the api for RVF/RVD fmin/fmax
,
frank . chang
,
12:09
[PATCH v5 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
,
frank . chang
,
12:09
[PATCH v5 0/2] add APIs to handle alternative sNaN propagation for fmax/fmin
,
frank . chang
,
12:09
[RFC PATCH v1 0/2] riscv: Add preliminary custom instruction support
,
Ruinland Chuan-Tzu Tsai
,
11:18
[RFC PATCH v1 2/2] Enable custom instruction suport for Andes A25 and AX25 CPU model
,
Ruinland Chuan-Tzu Tsai
,
11:15
[RFC PATCH v1 1/2] riscv: Add preliminary infra for custom instrcution handling
,
Ruinland Chuan-Tzu Tsai
,
11:15
[RFC PATCH v5 1/3] riscv: Adding Andes A25 and AX25 cpu models
,
Ruinland Chuan-Tzu Tsai
,
11:14
[RFC PATCH v5 3/3] riscv: Enable custom CSR support for Andes AX25 and A25 CPUs
,
Ruinland Chuan-Tzu Tsai
,
11:14
[RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()
,
Ruinland Chuan-Tzu Tsai
,
11:14
[RFC PATCH v5 0/3] riscv: Add preliminary custom CSR support
,
Ruinland Chuan-Tzu Tsai
,
11:14
Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp
,
Frédéric Pétrot
,
07:12
Re: [PATCH v1 9/9] hw/intc: sifive_plic: Cleanup remaining functions
,
Bin Meng
,
04:53
Re: [PATCH v1 8/9] hw/intc: sifive_plic: Cleanup the read function
,
Bin Meng
,
04:53
Re: [PATCH v1 7/9] hw/intc: sifive_plic: Cleanup the write function
,
Bin Meng
,
04:53
Re: [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
,
Igor Mammedov
,
04:48
Re: [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
,
Igor Mammedov
,
04:44
Re: [PATCH v2 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
,
Igor Mammedov
,
04:43
Re: [PATCH v1 6/9] hw/intc: sifive_plic: Add a reset function
,
Bin Meng
,
03:37
Re: [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function
,
Bin Meng
,
03:34
Re: [PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function
,
Bin Meng
,
03:32
Re: [PATCH v1 3/9] hw/intc: sifive_plic: Move the properties
,
Bin Meng
,
03:29
Re: [PATCH v1 2/9] hw/intc: Remove the Ibex PLIC
,
Bin Meng
,
03:28
Re: [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build
,
Bin Meng
,
03:27
Re: [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended
,
Alistair Francis
,
00:29
Re: [PATCH v8 39/78] target/riscv: rvv-1.0: whole register move instructions
,
Alistair Francis
,
00:27
Re: [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions
,
Alistair Francis
,
00:26
Re: [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions
,
Alistair Francis
,
00:24
October 20, 2021
Re: [PATCH v15 4/8] [RISCV_PM] Add J extension state description
,
Alistair Francis
,
23:56
Re: [PATCH v4 8/8] target/riscv: zfh: add Zfhmin cpu property
,
Alistair Francis
,
19:27
Re: [PATCH v4 8/8] target/riscv: zfh: add Zfhmin cpu property
,
Alistair Francis
,
19:26
Re: [PATCH v4 6/8] target/riscv: zfh: add Zfh cpu property
,
Alistair Francis
,
19:26
Re: [PATCH v4 2/2] target/riscv: change the api for RVF/RVD fmin/fmax
,
Alistair Francis
,
19:25
Re: [PATCH v3 20/21] target/riscv: adding 128-bit access functions for some csrs
,
Richard Henderson
,
19:18
Re: [PATCH v2 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
,
Alistair Francis
,
19:14
Re: [PATCH v2 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
,
Alistair Francis
,
19:13
Re: [PATCH v2 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
,
Alistair Francis
,
19:12
Re: [PATCH v2 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
,
Alistair Francis
,
19:12
Re: [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
,
Alistair Francis
,
19:11
Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp
,
Richard Henderson
,
19:10
Re: [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
,
Alistair Francis
,
19:06
Re: [PATCH v3 16/21] target/riscv: adding high part of some csrs
,
Richard Henderson
,
19:04
Re: [PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns
,
Richard Henderson
,
18:18
Re: [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support
,
Richard Henderson
,
17:53
Re: [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns
,
Richard Henderson
,
17:47
Re: [PATCH v3 16/21] target/riscv: adding high part of some csrs
,
Richard Henderson
,
17:39
Re: [PATCH v3 15/21] target/riscv: support for 128-bit M extension
,
Richard Henderson
,
16:58
Re: [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions
,
Richard Henderson
,
16:16
Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions
,
Frédéric Pétrot
,
15:18
Re: [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions
,
Richard Henderson
,
15:07
Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions
,
Richard Henderson
,
14:06
Re: [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions
,
Richard Henderson
,
13:59
Re: [PATCH v3 10/21] target/riscv: support for 128-bit loads and store
,
Richard Henderson
,
13:31
Re: [PATCH v3 09/21] target/riscv: moving some insns close to similar insns
,
Richard Henderson
,
11:11
Re: [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part
,
Richard Henderson
,
11:09
Re: [PATCH v3 01/21] memory: change define name for consistency
,
Philippe Mathieu-Daudé
,
11:08
Re: [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles
,
Richard Henderson
,
10:57
Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers
,
Richard Henderson
,
10:44
Re: [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers
,
Richard Henderson
,
10:14
Re: [PATCH v3 04/21] target/riscv: additional macros to check instruction support
,
Richard Henderson
,
10:08
Re: [PATCH v2 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
,
Philippe Mathieu-Daudé
,
09:02
Re: [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
,
Philippe Mathieu-Daudé
,
09:02
Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
,
Alistair Francis
,
07:03
[PATCH v15 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
,
Alexey Baturo
,
06:20
[PATCH v15 4/8] [RISCV_PM] Add J extension state description
,
Alexey Baturo
,
06:20
[PATCH v15 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Alexey Baturo
,
06:20
[PATCH v15 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs
,
Alexey Baturo
,
06:20
[PATCH v15 1/8] [RISCV_PM] Add J-extension into RISC-V
,
Alexey Baturo
,
06:20
[PATCH v15 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension
,
Alexey Baturo
,
06:19
[PATCH v15 8/8] [RISCV_PM] Allow experimental J-ext to be turned on
,
Alexey Baturo
,
06:19
[PATCH v15 0/8] RISC-V Pointer Masking implementation
,
Alexey Baturo
,
06:19
[PATCH v15 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
,
Alexey Baturo
,
06:19
Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
,
Igor Mammedov
,
04:32
Re: [PATCH v8 00/78] support vector extension v1.0
,
Alistair Francis
,
01:29
October 19, 2021
[PATCH v6 15/15] target/riscv: Compute mstatus.sd on demand
,
Richard Henderson
,
23:17
[PATCH v6 13/15] target/riscv: Use gen_shift*_per_ol for RVB, RVI
,
Richard Henderson
,
23:17
[PATCH v6 14/15] target/riscv: Use riscv_csrrw_debug for cpu_dump
,
Richard Henderson
,
23:17
[PATCH v6 12/15] target/riscv: Use gen_unary_per_ol for RVB
,
Richard Henderson
,
23:17
[PATCH v6 05/15] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
,
Richard Henderson
,
23:17
[PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64
,
Richard Henderson
,
23:17
[PATCH v6 03/15] target/riscv: Split misa.mxl and misa.ext
,
Richard Henderson
,
23:17
[PATCH v6 10/15] target/riscv: Use gen_arith_per_ol for RVM
,
Richard Henderson
,
23:17
[PATCH v6 09/15] target/riscv: Replace DisasContext.w with DisasContext.ol
,
Richard Henderson
,
23:17
[PATCH v6 06/15] target/riscv: Use REQUIRE_64BIT in amo_check64
,
Richard Henderson
,
23:17
[PATCH v6 04/15] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
Richard Henderson
,
23:17
[PATCH v6 07/15] target/riscv: Properly check SEW in amo_op
,
Richard Henderson
,
23:17
[PATCH v6 08/15] target/riscv: Replace is_32bit with get_xl/get_xlen
,
Richard Henderson
,
23:17
[PATCH v6 02/15] target/riscv: Create RISCVMXL enumeration
,
Richard Henderson
,
23:17
[PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
,
Richard Henderson
,
23:17
[PATCH v6 01/15] target/riscv: Move cpu_get_tb_cpu_state out of line
,
Richard Henderson
,
23:17
[PATCH v4 8/8] target/riscv: zfh: add Zfhmin cpu property
,
frank . chang
,
23:07
[PATCH v4 7/8] target/riscv: zfh: implement zfhmin extension
,
frank . chang
,
23:07
[PATCH v4 6/8] target/riscv: zfh: add Zfh cpu property
,
frank . chang
,
23:07
[PATCH v4 2/8] target/riscv: zfh: half-precision computational
,
frank . chang
,
23:07
[PATCH v4 5/8] target/riscv: zfh: half-precision floating-point classify
,
frank . chang
,
23:07
[PATCH v4 4/8] target/riscv: zfh: half-precision floating-point compare
,
frank . chang
,
23:07
[PATCH v4 3/8] target/riscv: zfh: half-precision convert and move
,
frank . chang
,
23:07
[PATCH v4 1/8] target/riscv: zfh: half-precision load and store
,
frank . chang
,
23:07
[PATCH v4 0/8] target/riscv: support Zfh, Zfhmin extension v0.1
,
frank . chang
,
23:07
Re: [PATCH v4 2/2] target/riscv: change the api for RVF/RVD fmin/fmax
,
Frank Chang
,
22:56
Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
21:56
[PATCH v2 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
21:41
[PATCH v2 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
21:41
[PATCH v2 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
21:41
[PATCH v2 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
21:41
[PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
21:41
[PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
21:41
[PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines
,
Bin Meng
,
21:41
Re: [PATCH v5 14/16] target/riscv: Align gprs and fprs in cpu_dump
,
Richard Henderson
,
19:10
Re: [PATCH v14 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
,
Alistair Francis
,
18:28
Re: [PATCH v5 16/16] target/riscv: Compute mstatus.sd on demand
,
Alistair Francis
,
18:13
Re: [PATCH v5 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump
,
Alistair Francis
,
18:12
Re: [PATCH v5 14/16] target/riscv: Align gprs and fprs in cpu_dump
,
Alistair Francis
,
18:11
Re: [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations
,
Richard Henderson
,
14:15
Re: [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values
,
Richard Henderson
,
14:00
[PATCH v5 16/16] target/riscv: Compute mstatus.sd on demand
,
Richard Henderson
,
11:25
[PATCH v5 12/16] target/riscv: Use gen_unary_per_ol for RVB
,
Richard Henderson
,
11:25
[PATCH v5 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump
,
Richard Henderson
,
11:25
[PATCH v5 14/16] target/riscv: Align gprs and fprs in cpu_dump
,
Richard Henderson
,
11:25
[PATCH v5 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI
,
Richard Henderson
,
11:25
[PATCH v5 11/16] target/riscv: Adjust trans_rev8_32 for riscv64
,
Richard Henderson
,
11:25
[PATCH v5 10/16] target/riscv: Use gen_arith_per_ol for RVM
,
Richard Henderson
,
11:25
[PATCH v5 07/16] target/riscv: Properly check SEW in amo_op
,
Richard Henderson
,
11:24
[PATCH v5 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
Richard Henderson
,
11:24
[PATCH v5 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol
,
Richard Henderson
,
11:24
[PATCH v5 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
,
Richard Henderson
,
11:24
[PATCH v5 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen
,
Richard Henderson
,
11:24
[PATCH v5 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64
,
Richard Henderson
,
11:24
[PATCH v5 03/16] target/riscv: Split misa.mxl and misa.ext
,
Richard Henderson
,
11:24
[PATCH v5 01/16] target/riscv: Move cpu_get_tb_cpu_state out of line
,
Richard Henderson
,
11:24
[PATCH v5 02/16] target/riscv: Create RISCVMXL enumeration
,
Richard Henderson
,
11:24
[PATCH v5 00/16] target/riscv: Rationalize XLEN and operand length
,
Richard Henderson
,
11:24
Re: [PATCH 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
08:57
[PATCH v3 20/21] target/riscv: adding 128-bit access functions for some csrs
,
Frédéric Pétrot
,
05:49
[PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns
,
Frédéric Pétrot
,
05:49
[PATCH v3 16/21] target/riscv: adding high part of some csrs
,
Frédéric Pétrot
,
05:49
[PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support
,
Frédéric Pétrot
,
05:49
[PATCH v3 15/21] target/riscv: support for 128-bit M extension
,
Frédéric Pétrot
,
05:49
[PATCH v3 21/21] target/riscv: support for 128-bit satp
,
Frédéric Pétrot
,
05:49
[PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns
,
Frédéric Pétrot
,
05:49
[PATCH v3 13/21] target/riscv: support for 128-bit shift instructions
,
Frédéric Pétrot
,
05:49
[PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions
,
Frédéric Pétrot
,
05:49
[PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions
,
Frédéric Pétrot
,
05:48
[PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions
,
Frédéric Pétrot
,
05:48
[PATCH v3 10/21] target/riscv: support for 128-bit loads and store
,
Frédéric Pétrot
,
05:48
[PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles
,
Frédéric Pétrot
,
05:48
[PATCH v3 08/21] target/riscv: adding accessors to the registers upper part
,
Frédéric Pétrot
,
05:48
[PATCH v3 01/21] memory: change define name for consistency
,
Frédéric Pétrot
,
05:48
[PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers
,
Frédéric Pétrot
,
05:48
[PATCH v3 09/21] target/riscv: moving some insns close to similar insns
,
Frédéric Pétrot
,
05:48
[PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers
,
Frédéric Pétrot
,
05:48
[PATCH v3 03/21] Int128.h: addition of a few 128-bit operations
,
Frédéric Pétrot
,
05:48
[PATCH v3 00/21] Adding partial support for 128-bit riscv target
,
Frédéric Pétrot
,
05:48
[PATCH v3 04/21] target/riscv: additional macros to check instruction support
,
Frédéric Pétrot
,
05:48
[PATCH v3 02/21] memory: add a few defines for octo (128-bit) values
,
Frédéric Pétrot
,
05:48
Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
,
Igor Mammedov
,
03:39
Re: [PATCH 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
,
Igor Mammedov
,
03:17
Re: [PATCH 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
,
Igor Mammedov
,
03:16
Re: [PATCH 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
,
Igor Mammedov
,
03:15
Re: [PATCH 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
,
Igor Mammedov
,
03:12
Re: [PATCH 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
,
Igor Mammedov
,
03:11
Re: [PATCH v14 4/8] [RISCV_PM] Add J extension state description
,
Alexey Baturo
,
03:03
Re: [PATCH v14 4/8] [RISCV_PM] Add J extension state description
,
Alistair Francis
,
02:53
October 18, 2021
Re: [PATCH v4 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump
,
Richard Henderson
,
22:55
Re: [PATCH v4 14/16] target/riscv: Align gprs and fprs in cpu_dump
,
LIU Zhiwei
,
22:42
Re: [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol
,
Richard Henderson
,
22:30
Re: [PATCH v1 2/2] target/riscv: Organise the CPU properties
,
Bin Meng
,
22:29
Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
,
Bin Meng
,
22:26
Re: [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol
,
LIU Zhiwei
,
22:25
Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
,
Alistair Francis
,
20:37
[PATCH v4 14/16] target/riscv: Align gprs and fprs in cpu_dump
,
Richard Henderson
,
20:01
[PATCH v4 16/16] target/riscv: Compute mstatus.sd on demand
,
Richard Henderson
,
20:01
[PATCH v4 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump
,
Richard Henderson
,
20:01
[PATCH v4 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI
,
Richard Henderson
,
20:01
[PATCH v4 11/16] target/riscv: Adjust trans_rev8_32 for riscv64
,
Richard Henderson
,
20:01
[PATCH v4 12/16] target/riscv: Use gen_unary_per_ol for RVB
,
Richard Henderson
,
20:01
[PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol
,
Richard Henderson
,
20:01
[PATCH v4 07/16] target/riscv: Properly check SEW in amo_op
,
Richard Henderson
,
20:01
[PATCH v4 10/16] target/riscv: Use gen_arith_per_ol for RVM
,
Richard Henderson
,
20:01
[PATCH v4 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
Richard Henderson
,
20:01
[PATCH v4 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen
,
Richard Henderson
,
20:01
[PATCH v4 03/16] target/riscv: Split misa.mxl and misa.ext
,
Richard Henderson
,
20:01
[PATCH v4 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
,
Richard Henderson
,
20:01
[PATCH v4 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64
,
Richard Henderson
,
20:01
[PATCH v4 02/16] target/riscv: Create RISCVMXL enumeration
,
Richard Henderson
,
20:01
[PATCH v4 00/16] target/riscv: Rationalize XLEN and operand length
,
Richard Henderson
,
20:01
[PATCH v4 01/16] target/riscv: Move cpu_get_tb_cpu_state out of line
,
Richard Henderson
,
20:01
Re: [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts
,
Alistair Francis
,
18:55
Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
12:00
Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
,
Philippe Mathieu-Daudé
,
11:51
[PATCH 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
11:38
[PATCH 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
11:38
[PATCH 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
11:38
[PATCH 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
11:38
[PATCH 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
11:38
[PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
,
Bin Meng
,
11:38
Re: [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts
,
Anup Patel
,
08:55
Re: [PATCH v3 05/14] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
,
LIU Zhiwei
,
07:55
Re: [PATCH v3 04/14] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
LIU Zhiwei
,
07:51
Re: [PATCH v3 03/14] target/riscv: Split misa.mxl and misa.ext
,
LIU Zhiwei
,
07:46
Re: [PATCH v8 00/78] support vector extension v1.0
,
LIU Zhiwei
,
05:35
Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
,
Philippe Mathieu-Daudé
,
05:30
Re: [PATCH v1 2/2] target/riscv: Organise the CPU properties
,
Frank Chang
,
05:12
Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
,
Frank Chang
,
05:12
Re: [PATCH v8 00/78] support vector extension v1.0
,
LIU Zhiwei
,
05:01
Re: [PATCH v2] hw/riscv: virt: bugfix the memory-backend-file command is invalid
,
Igor Mammedov
,
02:42
Re: [PATCH v8 00/78] support vector extension v1.0
,
Frank Chang
,
02:18
Re: [PATCH v8 00/78] support vector extension v1.0
,
Alistair Francis
,
02:13
Re: [PATCH v3 3/6] target/riscv: zfh: half-precision convert and move
,
Alistair Francis
,
02:11
Re: [PATCH v8 00/78] support vector extension v1.0
,
Frank Chang
,
02:09
Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand
,
Richard Henderson
,
02:05
Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
,
Alistair Francis
,
02:01
Re: [PATCH v8 00/78] support vector extension v1.0
,
Alistair Francis
,
02:00
Re: [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction
,
Alistair Francis
,
01:54
Re: [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions
,
Alistair Francis
,
01:53
Re: [PATCH v3 3/6] target/riscv: zfh: half-precision convert and move
,
Richard Henderson
,
01:53
Re: [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction
,
Alistair Francis
,
01:50
Re: [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction
,
Alistair Francis
,
01:47
Re: [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction
,
Alistair Francis
,
01:46
Re: [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions
,
Alistair Francis
,
01:44
Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand
,
Alistair Francis
,
01:39
Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
,
Richard Henderson
,
01:38
Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand
,
Richard Henderson
,
01:32
Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand
,
Alistair Francis
,
00:53
Re: [PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI
,
Alistair Francis
,
00:43
Re: [PATCH v3 12/14] target/riscv: Use gen_unary_per_ol for RVB
,
Alistair Francis
,
00:38
Re: [PATCH v3 10/14] target/riscv: Use gen_arith_per_ol for RVM
,
Alistair Francis
,
00:36
[PATCH v1 2/2] target/riscv: Organise the CPU properties
,
Alistair Francis
,
00:32
[PATCH v1 1/2] target/riscv: Remove some unused macros
,
Alistair Francis
,
00:32
Re: [PATCH v3 1/6] target/riscv: zfh: half-precision load and store
,
Alistair Francis
,
00:29
October 17, 2021
Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax
,
Frank Chang
,
23:51
[PATCH v1 9/9] hw/intc: sifive_plic: Cleanup remaining functions
,
Alistair Francis
,
22:41
[PATCH v1 8/9] hw/intc: sifive_plic: Cleanup the read function
,
Alistair Francis
,
22:40
[PATCH v1 7/9] hw/intc: sifive_plic: Cleanup the write function
,
Alistair Francis
,
22:40
[PATCH v1 6/9] hw/intc: sifive_plic: Add a reset function
,
Alistair Francis
,
22:40
[PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function
,
Alistair Francis
,
22:40
[PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function
,
Alistair Francis
,
22:39
[PATCH v1 3/9] hw/intc: sifive_plic: Move the properties
,
Alistair Francis
,
22:39
[PATCH v1 2/9] hw/intc: Remove the Ibex PLIC
,
Alistair Francis
,
22:39
[PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build
,
Alistair Francis
,
22:39
Re: [PATCH v2] hw/riscv: virt: bugfix the memory-backend-file command is invalid
,
Bin Meng
,
22:18
Re: [PATCH v3 1/6] target/riscv: zfh: half-precision load and store
,
Frank Chang
,
22:15
Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS
,
Alistair Francis
,
21:14
Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax
,
Alistair Francis
,
20:18
Re: [PATCH v3 6/6] target/riscv: zfh: implement zfhmin extension
,
Alistair Francis
,
20:05
Re: [PATCH v3 1/6] target/riscv: zfh: half-precision load and store
,
Alistair Francis
,
20:03
Re: [PATCH v3 5/6] target/riscv: zfh: half-precision floating-point classify
,
Alistair Francis
,
20:02
Re: [PATCH v3 4/6] target/riscv: zfh: half-precision floating-point compare
,
Alistair Francis
,
20:01
Re: [PATCH v3 3/6] target/riscv: zfh: half-precision convert and move
,
Alistair Francis
,
20:00
Re: [PATCH v3 2/6] target/riscv: zfh: half-precision computational
,
Alistair Francis
,
19:51
Re: [PATCH v3] hw/riscv: virt: Use machine->ram as the system memory
,
Alistair Francis
,
19:25
Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
,
Alistair Francis
,
18:56
Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS
,
Jose Martins
,
16:30
[PATCH v14 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
,
Alexey Baturo
,
13:27
[PATCH v14 8/8] [RISCV_PM] Allow experimental J-ext to be turned on
,
Alexey Baturo
,
13:27
[PATCH v14 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Alexey Baturo
,
13:27
[PATCH v14 4/8] [RISCV_PM] Add J extension state description
,
Alexey Baturo
,
13:27
[PATCH v14 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs
,
Alexey Baturo
,
13:27
[PATCH v14 0/8] RISC-V Pointer Masking implementation
,
Alexey Baturo
,
13:27
[PATCH v14 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
,
Alexey Baturo
,
13:27
[PATCH v14 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension
,
Alexey Baturo
,
13:27
[PATCH v14 1/8] [RISCV_PM] Add J-extension into RISC-V
,
Alexey Baturo
,
13:27
Re: [PATCH v13 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Alexey Baturo
,
13:21
Re: [PATCH v13 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
,
Alexey Baturo
,
13:14
Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax
,
Frank Chang
,
02:57
October 16, 2021
Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax
,
Frank Chang
,
20:55
Re: [PATCH v3 0/6] target/riscv: support Zfh, Zfhmin extension v0.1
,
Frank Chang
,
20:23
Re: [PATCH v3 0/6] target/riscv: support Zfh, Zfhmin extension v0.1
,
Richard Henderson
,
14:03
Re: [PATCH v4 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
,
Richard Henderson
,
13:59
Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax
,
Richard Henderson
,
13:56
[PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI
,
Richard Henderson
,
13:14
[PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand
,
Richard Henderson
,
13:14
[PATCH v3 10/14] target/riscv: Use gen_arith_per_ol for RVM
,
Richard Henderson
,
13:14
[PATCH v3 11/14] target/riscv: Adjust trans_rev8_32 for riscv64
,
Richard Henderson
,
13:14
[PATCH v3 12/14] target/riscv: Use gen_unary_per_ol for RVB
,
Richard Henderson
,
13:14
[PATCH v3 07/14] target/riscv: Properly check SEW in amo_op
,
Richard Henderson
,
13:14
[PATCH v3 09/14] target/riscv: Replace DisasContext.w with DisasContext.ol
,
Richard Henderson
,
13:14
[PATCH v3 01/14] target/riscv: Move cpu_get_tb_cpu_state out of line
,
Richard Henderson
,
13:14
[PATCH v3 02/14] target/riscv: Create RISCVMXL enumeration
,
Richard Henderson
,
13:14
[PATCH v3 06/14] target/riscv: Use REQUIRE_64BIT in amo_check64
,
Richard Henderson
,
13:14
[PATCH v3 03/14] target/riscv: Split misa.mxl and misa.ext
,
Richard Henderson
,
13:14
[PATCH v3 04/14] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
Richard Henderson
,
13:14
[PATCH v3 05/14] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
,
Richard Henderson
,
13:14
[PATCH v3 08/14] target/riscv: Replace is_32bit with get_xl/get_xlen
,
Richard Henderson
,
13:14
[PATCH v3 00/14] target/riscv: Rationalize XLEN and operand length
,
Richard Henderson
,
13:14
[PATCH v3 6/6] target/riscv: zfh: implement zfhmin extension
,
frank . chang
,
05:08
[PATCH v3 5/6] target/riscv: zfh: half-precision floating-point classify
,
frank . chang
,
05:08
[PATCH v3 4/6] target/riscv: zfh: half-precision floating-point compare
,
frank . chang
,
05:08
[PATCH v3 3/6] target/riscv: zfh: half-precision convert and move
,
frank . chang
,
05:08
[PATCH v3 2/6] target/riscv: zfh: half-precision computational
,
frank . chang
,
05:08
[PATCH v3 1/6] target/riscv: zfh: half-precision load and store
,
frank . chang
,
05:07
[PATCH v3 0/6] target/riscv: support Zfh, Zfhmin extension v0.1
,
frank . chang
,
05:07
[PATCH v4 2/2] target/riscv: change the api for RVF/RVD fmin/fmax
,
frank . chang
,
04:54
[PATCH v4 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
,
frank . chang
,
04:54
[PATCH v4 0/2] add APIs to handle alternative sNaN propagation for fmax/fmin
,
frank . chang
,
04:54
Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax
,
Frank Chang
,
04:52
Re: [PATCH v3 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
,
Frank Chang
,
04:51
October 15, 2021
[PATCH v3] hw/riscv: virt: Use machine->ram as the system memory
,
MingWang Li
,
23:09
Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
,
Richard Henderson
,
23:04
Re: [PATCH v13 7/7] [RISCV_PM] Allow experimental J-ext to be turned on
,
Richard Henderson
,
20:04
Re: [PATCH v13 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
,
Richard Henderson
,
20:03
Re: [PATCH v13 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
,
Richard Henderson
,
20:01
Re: [PATCH v13 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Richard Henderson
,
19:49
Re: [PATCH v5] hw/arm/virt: Don't create device-tree node for empty NUMA node
,
Richard Henderson
,
19:31
Re: [PATCH v2 6/6] target/riscv: zfh: implement zfhmin extension
,
Richard Henderson
,
17:14
Re: [PATCH v2 5/6] target/riscv: zfh: half-precision floating-point classify
,
Richard Henderson
,
17:11
Re: [PATCH v2 4/6] target/riscv: zfh: half-precision floating-point compare
,
Richard Henderson
,
17:10
Re: [PATCH v2 3/6] target/riscv: zfh: half-precision convert and move
,
Richard Henderson
,
17:08
Re: [PATCH v2 2/6] target/riscv: zfh: half-precision computational
,
Richard Henderson
,
16:42
Re: [PATCH v2 1/6] target/riscv: zfh: half-precision load and store
,
Richard Henderson
,
16:38
[PATCH v13 7/7] [RISCV_PM] Allow experimental J-ext to be turned on
,
Alexey Baturo
,
15:30
[PATCH v13 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
,
Alexey Baturo
,
15:30
[PATCH v13 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Alexey Baturo
,
15:30
[PATCH v13 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
,
Alexey Baturo
,
15:29
[PATCH v13 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension
,
Alexey Baturo
,
15:29
[PATCH v13 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs
,
Alexey Baturo
,
15:29
[PATCH v13 0/7] RISC-V Pointer Masking implementatio
,
Alexey Baturo
,
15:29
[PATCH v13 1/7] [RISCV_PM] Add J-extension into RISC-V
,
Alexey Baturo
,
15:29
Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax
,
Richard Henderson
,
13:06
Re: [PATCH v3 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
,
Richard Henderson
,
13:00
[PATCH v4] hw/arm/virt: Don't create device-tree node for empty NUMA node
,
Gavin Shan
,
09:49
Re: [PATCH v4] hw/arm/virt: Don't create device-tree node for empty NUMA node
,
Gavin Shan
,
09:49
[PATCH v5] hw/arm/virt: Don't create device-tree node for empty NUMA node
,
Gavin Shan
,
09:49
Re: [PATCH v3 1/2] numa: Require distance map when empty node exists
,
Gavin Shan
,
09:49
Re: [PATCH v3 1/2] numa: Require distance map when empty node exists
,
Gavin Shan
,
09:49
Re: [PATCH v5] hw/arm/virt: Don't create device-tree node for empty NUMA node
,
Andrew Jones
,
09:12
Re: [PATCH v2] hw/riscv: virt: bugfix the memory-backend-file command is invalid
,
Igor Mammedov
,
08:59
Re: [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
,
Alistair Francis
,
08:37
Re: [PATCH v4] hw/arm/virt: Don't create device-tree node for empty NUMA node
,
Andrew Jones
,
08:23
Re: [PATCH v2] hw/riscv: virt: bugfix the memory-backend-file command is invalid
,
Bin Meng
,
05:25
Re: [PATCH v8 00/78] support vector extension v1.0
,
Frank Chang
,
05:03
RE: [PATCH v2] hw/riscv: virt: bugfix the memory-backend-file command is invalid
,
limingwang (A)
,
04:52
Re: [PATCH v3 1/2] numa: Require distance map when empty node exists
,
Andrew Jones
,
04:34
[PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment
,
frank . chang
,
03:51
[PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
,
frank . chang
,
03:51
[PATCH v8 76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
,
frank . chang
,
03:51
[PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
,
frank . chang
,
03:51
[PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction
,
frank . chang
,
03:51
[PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
,
frank . chang
,
03:51
[PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs
,
frank . chang
,
03:51
[PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
,
frank . chang
,
03:51
[PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
,
frank . chang
,
03:51
[PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32
,
frank . chang
,
03:51
[PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs
,
frank . chang
,
03:50
[PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
,
frank . chang
,
03:50
[PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR
,
frank . chang
,
03:50
[PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
,
frank . chang
,
03:50
[PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
,
frank . chang
,
03:50
[PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function
,
frank . chang
,
03:50
[PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert
,
frank . chang
,
03:50
[PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
,
frank . chang
,
03:50
[PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum
,
frank . chang
,
03:50
[PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions
,
frank . chang
,
03:50
[PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction
,
frank . chang
,
03:50
[PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
,
frank . chang
,
03:50
[PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
,
frank . chang
,
03:50
[PATCH v8 55/78] target/riscv: rvv-1.0: single-width scaling shift instructions
,
frank . chang
,
03:50
[PATCH v8 54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions
,
frank . chang
,
03:50
[PATCH v8 53/78] target/riscv: rvv-1.0: single-width floating-point reduction
,
frank . chang
,
03:50
[PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
,
frank . chang
,
03:50
[PATCH v8 51/78] target/riscv: rvv-1.0: floating-point slide instructions
,
frank . chang
,
03:49
[PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions
,
frank . chang
,
03:49
[PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions
,
frank . chang
,
03:49
[PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions
,
frank . chang
,
03:49
[PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions
,
frank . chang
,
03:49
[PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
,
frank . chang
,
03:49
[PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions
,
frank . chang
,
03:49
[PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions
,
frank . chang
,
03:49
[PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
,
frank . chang
,
03:49
[PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions
,
frank . chang
,
03:49
[PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
,
frank . chang
,
03:49
[PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions
,
frank . chang
,
03:49
[PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions
,
frank . chang
,
03:49
[PATCH v8 39/78] target/riscv: rvv-1.0: whole register move instructions
,
frank . chang
,
03:49
[PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction
,
frank . chang
,
03:49
[PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions
,
frank . chang
,
03:49
[PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions
,
frank . chang
,
03:49
[PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended
,
frank . chang
,
03:49
[PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction
,
frank . chang
,
03:49
[PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction
,
frank . chang
,
03:49
[PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions
,
frank . chang
,
03:49
[PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction
,
frank . chang
,
03:48
[PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction
,
frank . chang
,
03:48
[PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction
,
frank . chang
,
03:48
[PATCH v8 28/78] target/riscv: rvv-1.0: floating-point classify instructions
,
frank . chang
,
03:48
[PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
,
frank . chang
,
03:48
[PATCH v8 27/78] target/riscv: rvv-1.0: floating-point square-root instruction
,
frank . chang
,
03:48
[PATCH v8 25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
,
frank . chang
,
03:48
[PATCH v8 24/78] target/riscv: rvv-1.0: load/store whole register instructions
,
frank . chang
,
03:48
[PATCH v8 23/78] target/riscv: rvv-1.0: fault-only-first unit stride load
,
frank . chang
,
03:48
[PATCH 23/76] target/riscv: rvv-1.0: amo operations
,
frank . chang
,
03:48
[PATCH v8 21/78] target/riscv: rvv-1.0: index load and store instructions
,
frank . chang
,
03:48
[PATCH v8 22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
,
frank . chang
,
03:48
[PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit stride load
,
frank . chang
,
03:48
[PATCH 21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
,
frank . chang
,
03:48
[PATCH v8 20/78] target/riscv: rvv-1.0: stride load and store instructions
,
frank . chang
,
03:48
[PATCH 20/76] target/riscv: rvv-1.0: index load and store instructions
,
frank . chang
,
03:48
[PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions
,
frank . chang
,
03:47
[PATCH v8 19/78] target/riscv: rvv-1.0: configure instructions
,
frank . chang
,
03:47
[PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions
,
frank . chang
,
03:47
[PATCH v8 15/78] target/riscv: rvv-1.0: update check functions
,
frank . chang
,
03:47
[PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions
,
frank . chang
,
03:47
[PATCH 18/76] target/riscv: rvv-1.0: configure instructions
,
frank . chang
,
03:47
[PATCH v8 14/78] target/riscv: rvv-1.0: add VMA and VTA
,
frank . chang
,
03:47
[PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function
,
frank . chang
,
03:47
[PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL
,
frank . chang
,
03:47
[PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations
,
frank . chang
,
03:47
[PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
,
frank . chang
,
03:47
[PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register
,
frank . chang
,
03:47
[PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register
,
frank . chang
,
03:47
[PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
,
frank . chang
,
03:47
[PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus VS field
,
frank . chang
,
03:47
[PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status
,
frank . chang
,
03:47
[PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field
,
frank . chang
,
03:47
[PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field
,
frank . chang
,
03:46
[PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field
,
frank . chang
,
03:46
[PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support
,
frank . chang
,
03:46
[PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
,
frank . chang
,
03:46
[PATCH v8 00/78] support vector extension v1.0
,
frank . chang
,
03:46
[PATCH v2 6/6] target/riscv: zfh: implement zfhmin extension
,
frank . chang
,
03:03
[PATCH v2 5/6] target/riscv: zfh: half-precision floating-point classify
,
frank . chang
,
03:03
[PATCH v2 4/6] target/riscv: zfh: half-precision floating-point compare
,
frank . chang
,
03:03
[PATCH v2 3/6] target/riscv: zfh: half-precision convert and move
,
frank . chang
,
03:03
[PATCH v2 2/6] target/riscv: zfh: half-precision computational
,
frank . chang
,
03:03
[PATCH v2 1/6] target/riscv: zfh: half-precision load and store
,
frank . chang
,
03:03
[PATCH v2 0/6] target/riscv: support Zfh, Zfhmin extension v0.1
,
frank . chang
,
03:03
[PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax
,
frank . chang
,
02:55
[PATCH v3 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
,
frank . chang
,
02:55
[PATCH RESEND v3 0/2] add APIs to handle alternative sNaN propagation for fmax/fmin
,
frank . chang
,
02:55
Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax
,
Frank Chang
,
02:52
Re: [PATCH v3 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
,
Frank Chang
,
02:52
Re: [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts
,
Alistair Francis
,
02:24
[PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax
,
frank . chang
,
02:12
[PATCH v3 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
,
frank . chang
,
02:11
Re: [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64
,
Alistair Francis
,
01:22
Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
,
Alistair Francis
,
01:20
Re: [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen
,
Alistair Francis
,
01:12
Re: [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op
,
Alistair Francis
,
01:10
Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
,
Alistair Francis
,
01:08
Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
Alistair Francis
,
01:06
Re: [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext
,
Alistair Francis
,
01:02
October 14, 2021
Re: [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
,
Richard Henderson
,
12:12
Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
Richard Henderson
,
12:01
Re: [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext
,
Richard Henderson
,
11:52
Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
,
Richard Henderson
,
11:39
Re: [PATCH v3 1/2] numa: Require distance map when empty node exists
,
Andrew Jones
,
11:36
Re: [PATCH v3 1/2] numa: Require distance map when empty node exists
,
Igor Mammedov
,
11:14
Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
,
Frédéric Pétrot
,
04:57
Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
,
LIU Zhiwei
,
04:40
Re: [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen
,
LIU Zhiwei
,
04:26
Re: [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
,
LIU Zhiwei
,
04:21
Re: [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext
,
LIU Zhiwei
,
03:53
Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
LIU Zhiwei
,
03:08
Re: [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op
,
LIU Zhiwei
,
01:56
Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
,
LIU Zhiwei
,
01:54
October 13, 2021
[PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI
,
Richard Henderson
,
16:51
[PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen
,
Richard Henderson
,
16:51
[PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
,
Richard Henderson
,
16:51
[PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64
,
Richard Henderson
,
16:51
[PATCH v2 07/13] target/riscv: Properly check SEW in amo_op
,
Richard Henderson
,
16:51
[PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB
,
Richard Henderson
,
16:51
[PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM
,
Richard Henderson
,
16:51
[PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
,
Richard Henderson
,
16:51
[PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
,
Richard Henderson
,
16:51
[PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
Richard Henderson
,
16:51
[PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext
,
Richard Henderson
,
16:51
[PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration
,
Richard Henderson
,
16:51
[PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line
,
Richard Henderson
,
16:51
[PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length
,
Richard Henderson
,
16:51
Re: [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
Richard Henderson
,
12:54
Re: [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
Frédéric Pétrot
,
12:46
Re: [PATCH v2] hw/riscv: virt: bugfix the memory-backend-file command is invalid
,
Bin Meng
,
10:40
Re: [RFC PATCH v2 04/16] softmmu/qdev-monitor: add error handling in qdev_set_id
,
Damien Hedde
,
10:30
Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration
,
LIU Zhiwei
,
08:18
Re: [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line
,
LIU Zhiwei
,
08:13
Re: [PATCH 10/13] target/riscv: Use gen_arith_per_ol for RVM
,
LIU Zhiwei
,
07:54
Re: [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64
,
LIU Zhiwei
,
07:45
Re: [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI
,
LIU Zhiwei
,
07:24
Re: [PATCH] target/riscv: csr: Implement mconfigptr CSR
,
Bin Meng
,
05:36
Re: [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB
,
LIU Zhiwei
,
04:31
Re: [RFC PATCH v2 12/16] add x-sysbus-mmio-map qmp command
,
Alistair Francis
,
03:16
Re: [RFC PATCH v2 11/16] softmmu/memory: add memory_region_try_add_subregion function
,
Alistair Francis
,
03:13
Re: [RFC PATCH v2 04/16] softmmu/qdev-monitor: add error handling in qdev_set_id
,
Alistair Francis
,
03:11
Re: [RFC PATCH v2 00/16] Initial support for machine creation via QMP
,
Mark Burton
,
02:07
October 12, 2021
Re: [RFC PATCH v2 09/16] hw/core/machine: Remove the dynamic sysbus devices type check
,
Alistair Francis
,
19:08
Re: [RFC PATCH v2 08/16] qdev-monitor: Check sysbus device type before creating it
,
Alistair Francis
,
18:42
Re: [RFC PATCH v2 06/16] qapi: Allow device_add to execute in machine initialized phase
,
Alistair Francis
,
18:25
Re: [RFC PATCH v2 03/16] qapi: Implement x-machine-init QMP command
,
Alistair Francis
,
18:19
Re: [RFC PATCH v2 00/16] Initial support for machine creation via QMP
,
Alistair Francis
,
18:16
Re: [RFC PATCH v2 02/16] qapi: Implement query-machine-phase QMP command
,
Alistair Francis
,
18:09
Re: [PATCH] target/riscv: line up all of the registers in the info register dump
,
Alistair Francis
,
03:39
October 11, 2021
[PATCH v2] hw/riscv: virt: bugfix the memory-backend-file command is invalid
,
MingWang Li
,
21:46
Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration
,
Alistair Francis
,
19:29
Re: [PATCH] hw/riscv: virt: bugfix the memory-backend-file command is invalid
,
Alistair Francis
,
19:28
Re: [PATCH] target/riscv: line up all of the registers in the info register dump
,
Alistair Francis
,
19:24
October 10, 2021
Re: [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length
,
Frédéric Pétrot
,
11:17
October 09, 2021
[PATCH] target/riscv: line up all of the registers in the info register dump
,
Travis Geiselbrecht
,
01:50
October 08, 2021
Re: [PATCH] target/riscv: csr: Implement mconfigptr CSR
,
Rahul Pathak
,
05:47
RE: [PATCH] hw/riscv: virt: bugfix the memory-backend-file command is invalid
,
limingwang (A)
,
02:45
October 07, 2021
Re: [PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
,
Alistair Francis
,
23:40
Re: [PATCH] hw/riscv: virt: bugfix the memory-backend-file command is invalid
,
Bin Meng
,
23:30
Re: [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line
,
Alistair Francis
,
22:28
Re: [PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
,
Richard Henderson
,
13:53
[PATCH 10/13] target/riscv: Use gen_arith_per_ol for RVM
,
Richard Henderson
,
13:48
[PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64
,
Richard Henderson
,
13:47
[PATCH 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
,
Richard Henderson
,
13:47
[PATCH 03/13] target/riscv: Split misa.mxl and misa.ext
,
Richard Henderson
,
13:47
[PATCH 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
,
Richard Henderson
,
13:47
[PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen
,
Richard Henderson
,
13:47
[PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB
,
Richard Henderson
,
13:47
[PATCH 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
,
Richard Henderson
,
13:47
[PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI
,
Richard Henderson
,
13:47
[PATCH 07/13] target/riscv: Properly check SEW in amo_op
,
Richard Henderson
,
13:47
[PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
,
Richard Henderson
,
13:47
[PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line
,
Richard Henderson
,
13:47
[PATCH 02/13] target/riscv: Create RISCVMXL enumeration
,
Richard Henderson
,
13:47
[RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length
,
Richard Henderson
,
13:47
[PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
,
frank . chang
,
04:18
Re: [PATCH v2 00/27] Adding partial support for 128-bit riscv target
,
Philippe Mathieu-Daudé
,
04:11
Re: [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values
,
Philippe Mathieu-Daudé
,
04:06
Re: [PATCH] target/riscv: csr: Implement mconfigptr CSR
,
Bin Meng
,
01:38
October 06, 2021
Re: [PATCH v4 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only
,
Alistair Francis
,
17:37
Re: [PATCH v4 17/41] linux-user/host/riscv: Improve host_signal_write
,
Alistair Francis
,
17:36
Re: [PATCH v4 15/41] linux-user/host/riscv: Populate host_signal.h
,
Alistair Francis
,
17:34
[PATCH v2 20/27] target/riscv: addition of the 'd' insns for 128-bit mult/div/rem
,
Frédéric Pétrot
,
17:30
[PATCH v2 27/27] target/riscv: support for 128-bit satp
,
Frédéric Pétrot
,
17:30
[PATCH v2 26/27] target/riscv: adding 128-bit access functions for some csrs
,
Frédéric Pétrot
,
17:30
[PATCH v2 24/27] target/riscv: modification of the trans_csrxx for 128-bit support
,
Frédéric Pétrot
,
17:30
[PATCH v2 25/27] target/riscv: actual functions to realize crs 128-bit insns
,
Frédéric Pétrot
,
17:30
[PATCH v2 23/27] target/riscv: helper functions to wrap calls to 128-bit csr insns
,
Frédéric Pétrot
,
17:30
[PATCH v2 22/27] target/riscv: adding high part of some csrs
,
Frédéric Pétrot
,
17:30
[PATCH v2 21/27] target/riscv: div and rem insns on 128-bit
,
Frédéric Pétrot
,
17:30
[PATCH v2 17/27] target/riscv: 128-bit double word integer arithmetic instructions
,
Frédéric Pétrot
,
17:30
[PATCH v2 14/27] target/riscv: 128-bit support for instructions using gen_arith/gen_logic
,
Frédéric Pétrot
,
17:30
[PATCH v2 19/27] target/riscv: support for 128-bit base multiplications insns
,
Frédéric Pétrot
,
17:30
[PATCH v2 18/27] target/riscv: 128-bit double word integer shift instructions
,
Frédéric Pétrot
,
17:30
[PATCH v2 13/27] target/riscv: rename a few gen function helpers
,
Frédéric Pétrot
,
17:30
[PATCH v2 15/27] target/riscv: 128-bit support for instructions using gen_shift
,
Frédéric Pétrot
,
17:30
[PATCH v2 16/27] target/riscv: support for 128-bit loads and store
,
Frédéric Pétrot
,
17:30
[PATCH v2 12/27] target/riscv: moving some insns close to similar insns
,
Frédéric Pétrot
,
17:30
[PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers
,
Frédéric Pétrot
,
17:30
[PATCH v2 10/27] target/riscv: adding accessors to the registers upper part
,
Frédéric Pétrot
,
17:29
[PATCH v2 08/27] target/riscv: refactoring calls to gen_shift
,
Frédéric Pétrot
,
17:29
[PATCH v2 07/27] target/riscv: refactoring calls to gen_arith
,
Frédéric Pétrot
,
17:29
[PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles
,
Frédéric Pétrot
,
17:29
[PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers
,
Frédéric Pétrot
,
17:29
[PATCH v2 02/27] Int128.h: addition of a few 128-bit operations
,
Frédéric Pétrot
,
17:29
[PATCH v2 04/27] target/riscv: array for the 64 upper bits of 128-bit registers
,
Frédéric Pétrot
,
17:29
[PATCH v2 05/27] target/riscv: additional macros to check instruction support
,
Frédéric Pétrot
,
17:29
[PATCH v2 03/27] target/riscv: adding upper 64 bits for misa
,
Frédéric Pétrot
,
17:29
[PATCH v2 01/27] memory: add a few defines for octo (128-bit) values
,
Frédéric Pétrot
,
17:29
[PATCH v2 00/27] Adding partial support for 128-bit riscv target
,
Frédéric Pétrot
,
17:29
[PATCH v4 17/41] linux-user/host/riscv: Improve host_signal_write
,
Richard Henderson
,
13:23
[PATCH v4 15/41] linux-user/host/riscv: Populate host_signal.h
,
Richard Henderson
,
13:23
[PATCH v4 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only
,
Richard Henderson
,
13:23
October 04, 2021
Re: [RFC PATCH v2 00/16] Initial support for machine creation via QMP
,
Damien Hedde
,
11:56
October 03, 2021
[PATCH] target/riscv: csr: Implement mconfigptr CSR
,
Rahul Pathak
,
07:29
October 02, 2021
Re: [PATCH v3 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only
,
Philippe Mathieu-Daudé
,
10:27
October 01, 2021
[PATCH v3 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only
,
Richard Henderson
,
13:12
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