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[PATCH v3 09/21] target/riscv: moving some insns close to similar insns
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From: |
Frédéric Pétrot |
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Subject: |
[PATCH v3 09/21] target/riscv: moving some insns close to similar insns |
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Date: |
Tue, 19 Oct 2021 11:48:00 +0200 |
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
where they more logically belong.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++-------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index ed138f748e..5c2a117a70 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -175,6 +175,18 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
return gen_load(ctx, a, MO_TEUW);
}
+static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
+{
+ REQUIRE_64BIT(ctx);
+ return gen_load(ctx, a, MO_TEUL);
+}
+
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+ REQUIRE_64BIT(ctx);
+ return gen_load(ctx, a, MO_TEQ);
+}
+
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -205,18 +217,6 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
return gen_store(ctx, a, MO_TESL);
}
-static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
-{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEUL);
-}
-
-static bool trans_ld(DisasContext *ctx, arg_ld *a)
-{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEQ);
-}
-
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
REQUIRE_64BIT(ctx);
@@ -315,11 +315,6 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
}
-static bool trans_xor(DisasContext *ctx, arg_xor *a)
-{
- return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl);
-}
-
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
@@ -330,6 +325,11 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
}
+static bool trans_xor(DisasContext *ctx, arg_xor *a)
+{
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl);
+}
+
static bool trans_or(DisasContext *ctx, arg_or *a)
{
return gen_logic(ctx, a, EXT_NONE, tcg_gen_or_tl);
--
2.33.0
- [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values, (continued)
- [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values, Frédéric Pétrot, 2021/10/19
- [PATCH v3 04/21] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/19
- [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/19
- [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/19
- [PATCH v3 09/21] target/riscv: moving some insns close to similar insns,
Frédéric Pétrot <=
- [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/19
- [PATCH v3 01/21] memory: change define name for consistency, Frédéric Pétrot, 2021/10/19
- [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/19
- [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/19
- [PATCH v3 10/21] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/19