Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask

qemu-riscv

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Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask

From:	Richard Henderson
Subject:	Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask
Date:	Wed, 10 Nov 2021 15:43:38 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 11/10/21 3:08 PM, LIU Zhiwei wrote:

You'll want to update the translator to use these new fields instead of using the[msu]pmmask / [msu]pmbase fields directly. (Which means that we will have fewer tcgvariables, and need not copy the "current" into DisasContext.)
Do you mean we can remove the global TCG variables pm_mask[] and pc_base[]?
If then how to transport env->cur_pmmask and env->cur_pmbase to DisasContext?

I mean replace the array of pm_mask/pm_base with scalar variables. Remove the cached arrayvalue in DisasContext, and use global variables for the tcg variables like we do foreverything else.

r~

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Re: [PATCH v2 05/14] target/riscv: Calculate address according to XLEN, (continued)
- [PATCH v2 06/14] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/10
- [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN, Richard Henderson, 2021/11/10
- [PATCH v2 08/14] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/10
- [PATCH v2 09/14] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 09/14] target/riscv: Relax debug check for pm write, Richard Henderson, 2021/11/10
- [PATCH v2 10/14] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask, Richard Henderson, 2021/11/10
    - Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/10
    - Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask, Richard Henderson <=
- [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN, Richard Henderson, 2021/11/10
- [PATCH v2 12/14] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, Richard Henderson, 2021/11/10
    - Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/10
    - Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, Richard Henderson, 2021/11/10
- [PATCH v2 13/14] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 13/14] target/riscv: Don't save pc when exception return, Richard Henderson, 2021/11/10
- [PATCH v2 14/14] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 14/14] target/riscv: Enable uxl field write, Richard Henderson, 2021/11/10

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