qemu-riscv (date)

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qemu-riscv (date)

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Last Modified: Mon Nov 29 2021 09:33:00 -0500
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November 29, 2021
- Re: [PATCH v6 03/18] qemu/int128: addition of div/rem 128-bit operations, Richard Henderson, 09:33
- Re: [PATCH v6 03/18] qemu/int128: addition of div/rem 128-bit operations, Frédéric Pétrot, 09:27
- Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 08:24
- Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target, Richard Henderson, 07:13
- Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target, Richard Henderson, 05:47
- Re: [PATCH v6 03/18] qemu/int128: addition of div/rem 128-bit operations, Richard Henderson, 05:07
November 28, 2021
- Re: [PATCH v10 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, Alistair Francis, 22:17
- [PATCH v10 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 22:15
- [PATCH v10 56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 22:14
- [PATCH v10 53/77] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 22:14
- [PATCH v10 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 22:13
- [PATCH v10 48/77] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 22:13
- [PATCH v10 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 22:13
- [PATCH v10 13/77] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 22:13
- [PATCH v10 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, frank . chang, 22:10
- [PATCH v10 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment, frank . chang, 22:10
- [PATCH v10 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, frank . chang, 22:10
- [PATCH v10 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 22:10
- [PATCH v10 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 22:10
- [PATCH v10 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 22:10
- [PATCH v10 72/77] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 22:10
- [PATCH v10 70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 22:10
- [PATCH v10 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 22:10
- [PATCH v10 06/77] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 22:10
- [PATCH v10 68/77] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 22:10
- [PATCH v10 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 22:09
- [PATCH v10 66/77] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 22:09
- [PATCH v10 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 22:09
- [PATCH v10 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 22:09
- [PATCH v10 60/77] target/riscv: introduce floating-point rounding mode enum, frank . chang, 22:09
- [PATCH v10 63/77] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 22:09
- [PATCH v10 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 22:09
- [PATCH v10 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 22:09
- [PATCH v10 59/77] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 22:09
- [PATCH v10 58/77] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 22:08
- [PATCH v10 57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 22:08
- [PATCH v10 55/77] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 22:08
- [PATCH v10 54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 22:08
- [PATCH v10 51/77] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 22:08
- [PATCH v10 50/77] target/riscv: rvv-1.0: slide instructions, frank . chang, 22:07
- [PATCH v10 49/77] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 22:07
- [PATCH v10 47/77] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 22:07
- [PATCH v10 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 22:07
- [PATCH v10 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 22:07
- [PATCH v10 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 22:07
- [PATCH v10 42/77] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 22:07
- [PATCH v10 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 22:07
- [PATCH v10 40/77] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 22:07
- [PATCH v10 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 22:07
- [PATCH v10 39/77] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 22:06
- [PATCH v10 37/77] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 22:06
- [PATCH v10 36/77] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 22:06
- [PATCH v10 35/77] target/riscv: rvv-1.0: register gather instructions, frank . chang, 22:06
- [PATCH v10 34/77] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 22:06
- [PATCH v10 33/77] target/riscv: rvv-1.0: element index instruction, frank . chang, 22:06
- [PATCH v10 32/77] target/riscv: rvv-1.0: iota instruction, frank . chang, 22:06
- [PATCH v10 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 22:06
- [PATCH v10 29/77] target/riscv: rvv-1.0: count population in mask instruction, frank . chang, 22:06
- [PATCH v10 28/77] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 22:06
- [PATCH v10 27/77] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 22:06
- [PATCH v10 26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 22:05
- [PATCH v10 25/77] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 22:05
- [PATCH v10 24/77] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 22:05
- [PATCH v10 23/77] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 22:05
- [PATCH v10 20/77] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 22:05
- [PATCH v10 22/77] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 22:05
- [PATCH v10 21/77] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 22:05
- [PATCH v10 19/77] target/riscv: rvv-1.0: configure instructions, frank . chang, 22:05
- [PATCH v10 18/77] target/riscv: rvv-1.0: remove amo operations instructions, frank . chang, 22:05
- [PATCH v10 17/77] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 22:05
- [PATCH v10 16/77] target/riscv: introduce more imm value modes in translator functions, frank . chang, 22:05
- [PATCH v10 15/77] target/riscv: rvv-1.0: update check functions, frank . chang, 22:04
- [PATCH v10 14/77] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 22:04
- [PATCH v10 12/77] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 22:04
- [PATCH v10 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 22:04
- [PATCH v10 10/77] target/riscv: rvv-1.0: add vlenb register, frank . chang, 22:04
- [PATCH v10 08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 22:04
- [PATCH v10 09/77] target/riscv: rvv-1.0: add vcsr register, frank . chang, 22:04
- [PATCH v10 07/77] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 22:04
- [PATCH v10 05/77] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 22:04
- [PATCH v10 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, frank . chang, 22:04
- [PATCH v10 03/77] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 22:04
- [PATCH v10 02/77] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 22:04
- [PATCH v10 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 22:03
- [PATCH v10 00/77] support vector extension v1.0, frank . chang, 22:03
- [PATCH v6 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 08:58
- [PATCH v6 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 08:58
- [PATCH v6 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 08:58
- [PATCH v6 10/18] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 08:58
- [PATCH v6 11/18] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 08:58
- [PATCH v6 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 08:58
- [PATCH v6 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 08:58
- [PATCH v6 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 08:58
- [PATCH v6 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 08:58
- [PATCH v6 07/18] target/riscv: setup everything for rv64 to support rv128 execution, Frédéric Pétrot, 08:58
- [PATCH v6 00/18] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 08:58
- [PATCH v6 01/18] exec/memop: Adding signedness to quad definitions, Frédéric Pétrot, 08:58
- [PATCH v6 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 08:58
- [PATCH v6 04/18] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 08:58
- [PATCH v6 08/18] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 08:58
- [PATCH v6 03/18] qemu/int128: addition of div/rem 128-bit operations, Frédéric Pétrot, 08:58
- [PATCH v6 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, Frédéric Pétrot, 08:58
- [PATCH v6 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 08:58
- [PATCH v6 02/18] exec/memop: Adding signed quad and octo defines, Frédéric Pétrot, 08:58
- [RFC PATCH 1/3] target/riscv: add support for svnapot extension, liweiwei, 08:53
- [RFC PATCH 3/3] target/riscv: add support for svpbmt extension, liweiwei, 08:53
- [RFC PATCH 2/3] target/riscv: add support for svinval extension, liweiwei, 08:53
- [RFC PATCH 0/3] support subsets of virtual memory extension, liweiwei, 08:53
November 26, 2021
- Re: [PATCH v5 20/22] target/riscv: Adjust vector address with mask, Richard Henderson, 06:34
- Re: [PATCH v5 10/22] target/riscv: Create current pm fields in env, Richard Henderson, 06:31
- Re: [PATCH v5 04/22] target/riscv: Create xl field in env, Richard Henderson, 06:26
- Re: [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl, Richard Henderson, 06:20
November 25, 2021
- Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 09:44
- Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles, Alistair Francis, 06:47
- [PATCH v5 22/22] target/riscv: Enable uxl field write, LIU Zhiwei, 02:52
- [PATCH v5 21/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 02:51
- [PATCH v5 20/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 02:51
- [PATCH v5 19/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 02:50
- [PATCH v5 18/22] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 02:49
- [PATCH v5 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 02:49
- [PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 02:48
- [PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 02:48
- [PATCH v5 14/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 02:47
- [PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 02:46
- [PATCH v5 12/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 02:46
- [PATCH v5 11/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 02:45
- [PATCH v5 10/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 02:45
- [PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 02:44
- [PATCH v5 08/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 02:44
- [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 02:43
- [PATCH v5 06/22] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 02:43
- [PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 02:42
- [PATCH v5 04/22] target/riscv: Create xl field in env, LIU Zhiwei, 02:42
- [PATCH v5 03/22] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 02:41
- [PATCH v5 02/22] target/riscv: Don't save pc when exception return, LIU Zhiwei, 02:41
- [PATCH v5 00/22] Support UXL filed in xstatus, LIU Zhiwei, 02:41
- [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl, LIU Zhiwei, 02:40
November 24, 2021
- Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles, Philippe Mathieu-Daudé, 02:33
- Re: [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines, Philippe Mathieu-Daudé, 02:22
- Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 01:56
- Re: [PATCH v5 15/18] target/riscv: adding high part of some csrs, Alistair Francis, 01:23
- Re: [PATCH v5 11/18] target/riscv: support for 128-bit U-type instructions, Alistair Francis, 01:21
- Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions, Alistair Francis, 01:14
- Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles, Alistair Francis, 01:12
November 23, 2021
- Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Alistair Francis, 06:09
- Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 05:59
- Re: [PATCH v2 0/5] Check PMP rules num before propagation, LIU Zhiwei, 04:12
- [PATCH v3 1/1] target/riscv: Fix PMP propagation for tlb, LIU Zhiwei, 04:09
- Re: [PATCH v2 1/5] target/riscv: Check PMP rules num before propagation, Alistair Francis, 01:18
- Re: [PATCH v1 01/12] update-linux-headers: Add asm-riscv/kvm.h, Alistair Francis, 01:13
- Re: [PATCH v5 04/18] target/riscv: additional macros to check instruction support, Alistair Francis, 01:12
- Re: [PATCH v5 08/18] target/riscv: moving some insns close to similar insns, Alistair Francis, 01:11
- Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Alistair Francis, 01:10
- Re: [PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, Alistair Francis, 01:08
- Re: [PATCH v5 03/18] qemu/int128: addition of div/rem 128-bit operations, Alistair Francis, 01:05
November 22, 2021
- [PATCH v2 5/5] target/riscv: Modify return and parameter type for pmp_adjust_tlb_size, LIU Zhiwei, 06:05
- [PATCH v2 4/5] target/riscv: Rename pmp_is_range_in_tlb, LIU Zhiwei, 06:05
- [PATCH v2 3/5] target/riscv: Discard return value for pmp_is_range_in_tlb, LIU Zhiwei, 06:04
- [PATCH v2 2/5] target/riscv: Give a more generic size for tlb, LIU Zhiwei, 06:03
- [PATCH v2 1/5] target/riscv: Check PMP rules num before propagation, LIU Zhiwei, 06:03
- [PATCH v2 0/5] Check PMP rules num before propagation, LIU Zhiwei, 06:02
- Re: [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines, Alistair Francis, 00:24
November 21, 2021
- Re: [RFC PATCH v2 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*, Alistair Francis, 20:58
- Re: [RFC PATCH-for-6.2?] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset, Alistair Francis, 19:45
- Re: [PATCH for-6.2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE, Alistair Francis, 19:45
November 20, 2021
- Re: [PATCH v1 12/12] target/riscv: Support virtual time context synchronization, Richard Henderson, 17:35
- Re: [PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu, Richard Henderson, 17:19
- Re: [PATCH v1 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Philippe Mathieu-Daudé, 07:25
- [PATCH v1 12/12] target/riscv: Support virtual time context synchronization, Yifei Jiang, 02:47
- [PATCH v1 11/12] target/riscv: Implement virtual time adjusting with vm state changing, Yifei Jiang, 02:47
- [PATCH v1 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer, Yifei Jiang, 02:47
- [PATCH v1 09/12] target/riscv: Add host cpu type, Yifei Jiang, 02:47
- [PATCH v1 07/12] target/riscv: Support setting external interrupt by KVM, Yifei Jiang, 02:47
- [PATCH v1 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Yifei Jiang, 02:47
- [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers, Yifei Jiang, 02:47
- [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers, Yifei Jiang, 02:47
- [PATCH v1 06/12] target/riscv: Support start kernel directly by KVM, Yifei Jiang, 02:47
- [PATCH v1 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface, Yifei Jiang, 02:47
- [PATCH v1 01/12] update-linux-headers: Add asm-riscv/kvm.h, Yifei Jiang, 02:47
- [PATCH v1 00/12] Add riscv kvm accel support, Yifei Jiang, 02:47
- [PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu, Yifei Jiang, 02:47
November 19, 2021
- Re: [PATCH v4 00/20] Support UXL filed in xstatus, LIU Zhiwei, 08:44
- Re: [PATCH for-6.2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE, Alistair Francis, 08:11
- Re: [RFC PATCH-for-6.2?] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset, Alistair Francis, 08:08
- Re: [PATCH v2 01/13] hw/sd/ssi-sd: Do not create SD card within controller's realize, Alistair Francis, 08:05
- Re: [PATCH v2 02/13] hw: Replace trivial drive_get_next() by drive_get(), Alistair Francis, 08:02
- Re: [PATCH] target/riscv: Check PMP rules num before propagation, Alistair Francis, 07:59
- Re: [PATCH v4 00/20] Support UXL filed in xstatus, Alistair Francis, 07:57
- Re: [PATCH v4 20/20] target/riscv: Enable uxl field write, Alistair Francis, 07:56
- Re: [PATCH v4 18/20] target/riscv: Adjust vector address with mask, Alistair Francis, 07:47
- Re: [PATCH v4 17/20] target/riscv: Fix check range for first fault only, Alistair Francis, 07:42
- Re: [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN, Alistair Francis, 07:41
- Re: [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN, Alistair Francis, 07:35
- Re: [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE, Alistair Francis, 07:34
- Re: [PATCH for-6.2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE, Markus Armbruster, 06:31
- Re: [PATCH for-6.2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE, Philippe Mathieu-Daudé, 06:03
- Re: [PATCH for-6.2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE, Thomas Huth, 06:02
- [RFC PATCH-for-6.2?] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset, Philippe Mathieu-Daudé, 05:48
- Re: [PATCH for-6.2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE, Philippe Mathieu-Daudé, 05:40
- [PATCH for-6.2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE, Thomas Huth, 05:26
November 18, 2021
- Re: [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE, Alistair Francis, 23:56
- Re: [PATCH v4 12/20] target/riscv: Split out the vill from vtype, Alistair Francis, 23:56
- Re: [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base, Alistair Francis, 23:51
- Re: [PATCH v4 10/20] target/riscv: Calculate address according to XLEN, Alistair Francis, 23:32
- Re: [PATCH v4 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base], Alistair Francis, 23:29
- Re: [PATCH v4 08/20] target/riscv: Create current pm fields in env, Alistair Francis, 23:23
November 17, 2021
- Re: [PATCH v2 01/13] hw/sd/ssi-sd: Do not create SD card within controller's realize, Philippe Mathieu-Daudé, 14:45
- [PATCH v2 02/13] hw: Replace trivial drive_get_next() by drive_get(), Markus Armbruster, 11:34
- [PATCH v2 01/13] hw/sd/ssi-sd: Do not create SD card within controller's realize, Markus Armbruster, 11:34
- Re: [PATCH v2 6/7] target/riscv: cpu: Enable native debug feature on virt and sifive_u CPUs, Bin Meng, 04:51
November 16, 2021
- Re: [PATCH v2 6/7] target/riscv: cpu: Enable native debug feature on virt and sifive_u CPUs, Alistair Francis, 19:58
- Re: [PATCH v2 5/7] target/riscv: csr: Hook debug CSR read/write, Alistair Francis, 19:57
- Re: [PATCH v2 3/7] target/riscv: debug: Implement debug related TCGCPUOps, Alistair Francis, 19:55
- Re: [PATCH v2 2/7] target/riscv: machine: Add debug state description, Alistair Francis, 19:50
- Re: [PATCH] target/riscv: Check PMP rules num before propagation, LIU Zhiwei, 19:43
- Re: [PATCH] target/riscv: Check PMP rules num before propagation, Alistair Francis, 19:03
- Re: [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 11:08
- [PATCH] target/riscv: Check PMP rules num before propagation, LIU Zhiwei, 10:11
- Re: [PATCH RFC 2/2] hw: Replace drive_get_next() by drive_get(), Cédric Le Goater, 07:14
- Re: [PATCH RFC 2/2] hw: Replace drive_get_next() by drive_get(), Markus Armbruster, 04:30
- Re: [PATCH RFC 2/2] hw: Replace drive_get_next() by drive_get(), Cédric Le Goater, 03:52
- [RFC PATCH v2 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*, liweiwei, 03:08
- [RFC PATCH v2 5/7] target/riscv: rvk: add CSR support for Zkr, liweiwei, 03:08
- [RFC PATCH v2 4/7] target/riscv: rvk: add implementation of instructions for Zk*, liweiwei, 03:07
- [RFC PATCH v2 6/7] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions, liweiwei, 03:07
- [RFC PATCH v2 7/7] target/riscv: rvk: expose zbk* and zk* properties, liweiwei, 03:07
- [RFC PATCH v2 2/7] target/riscv: rvk: add implementation of instructions for Zbk*, liweiwei, 03:07
- [RFC PATCH v2 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto, liweiwei, 03:07
- [RFC PATCH v2 0/7] support subsets of scalar crypto extension, liweiwei, 03:07
- Re: [PATCH RFC 2/2] hw: Replace drive_get_next() by drive_get(), Markus Armbruster, 02:47
November 15, 2021
- Re: [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN, Alistair Francis, 22:14
- Re: [PATCH v4 06/20] target/riscv: Relax debug check for pm write, Alistair Francis, 22:13
- Re: [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen, Alistair Francis, 22:13
- Re: [PATCH v9 68/76] target/riscv: gdb: support vector registers for rv64 & rv32, Alistair Francis, 19:13
- Re: [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write, Alistair Francis, 19:09
- Re: [PATCH v9 74/76] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, Alistair Francis, 19:08
- Re: [PATCH v9 73/76] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), Alistair Francis, 19:06
- Re: [PATCH v9 67/76] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, Alistair Francis, 18:56
- Re: [PATCH v9 66/76] target/riscv: rvv-1.0: implement vstart CSR, Alistair Francis, 18:55
- Re: [PATCH RFC 2/2] hw: Replace drive_get_next() by drive_get(), Philippe Mathieu-Daudé, 16:15
- Re: [PATCH RFC 0/2] Eliminate drive_get_next(), Markus Armbruster, 11:01
- Re: [PATCH RFC 2/2] hw: Replace drive_get_next() by drive_get(), Markus Armbruster, 10:57
- Re: [PATCH RFC 0/2] Eliminate drive_get_next(), Peter Maydell, 09:06
- Re: [PATCH RFC 2/2] hw: Replace drive_get_next() by drive_get(), Philippe Mathieu-Daudé, 08:59
- Re: [PATCH RFC 1/2] hw/sd/ssi-sd: Do not create SD card within controller's realize, Markus Armbruster, 08:49
- Re: [PATCH RFC 2/2] hw: Replace drive_get_next() by drive_get(), Markus Armbruster, 08:48
- Re: [PATCH RFC 1/2] hw/sd/ssi-sd: Do not create SD card within controller's realize, Peter Maydell, 08:46
- Re: [PATCH RFC 2/2] hw: Replace drive_get_next() by drive_get(), Peter Maydell, 08:44
- [PATCH RFC 2/2] hw: Replace drive_get_next() by drive_get(), Markus Armbruster, 07:55
- [PATCH RFC 0/2] Eliminate drive_get_next(), Markus Armbruster, 07:55
- [PATCH RFC 1/2] hw/sd/ssi-sd: Do not create SD card within controller's realize, Markus Armbruster, 07:55
- Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions, Richard Henderson, 03:30
- Re: [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Richard Henderson, 03:29
- Re: [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines, Richard Henderson, 03:02
November 14, 2021
- Re: [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN, Alistair Francis, 23:28
- Re: [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN, Alistair Francis, 23:27
- Re: [PATCH v4 01/20] target/riscv: Don't save pc when exception return, Alistair Francis, 23:25
- Re: [PATCH v5 01/18] exec/memop: Adding signedness to quad definitions, Richard Henderson, 07:49
November 12, 2021
- [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 10:00
- [PATCH v5 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 10:00
- [PATCH v5 11/18] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 10:00
- [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 10:00
- [PATCH v5 08/18] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 10:00
- [PATCH v5 00/18] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 10:00
- [PATCH v5 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 10:00
- [PATCH v5 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 10:00
- [PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, Frédéric Pétrot, 10:00
- [PATCH v5 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 10:00
- [PATCH v5 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 10:00
- [PATCH v5 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 10:00
- [PATCH v5 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 10:00
- [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 10:00
- [PATCH v5 04/18] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 10:00
- [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 10:00
- [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines, Frédéric Pétrot, 10:00
- [PATCH v5 01/18] exec/memop: Adding signedness to quad definitions, Frédéric Pétrot, 10:00
- [PATCH v5 03/18] qemu/int128: addition of div/rem 128-bit operations, Frédéric Pétrot, 10:00
November 11, 2021
- Re: [PATCH v4 20/20] target/riscv: Enable uxl field write, Richard Henderson, 13:24
- Re: [PATCH v3 20/20] target/riscv: Enable uxl field write, Richard Henderson, 13:20
- [PATCH v4 20/20] target/riscv: Enable uxl field write, LIU Zhiwei, 11:02
- [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 11:01
- [PATCH v4 18/20] target/riscv: Adjust vector address with mask, LIU Zhiwei, 11:01
- [PATCH v4 17/20] target/riscv: Fix check range for first fault only, LIU Zhiwei, 11:01
- [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 11:00
- [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 10:59
- [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 10:59
- [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 10:58
- [PATCH v4 12/20] target/riscv: Split out the vill from vtype, LIU Zhiwei, 10:58
- [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 10:57
- [PATCH v4 10/20] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 10:57
- [PATCH v4 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 10:56
- [PATCH v4 08/20] target/riscv: Create current pm fields in env, LIU Zhiwei, 10:56
- [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 10:55
- [PATCH v4 06/20] target/riscv: Relax debug check for pm write, LIU Zhiwei, 10:55
- [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 10:54
- [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 10:54
- [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 10:53
- [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 10:53
- [PATCH v4 01/20] target/riscv: Don't save pc when exception return, LIU Zhiwei, 10:52
- [PATCH v4 00/20] Support UXL filed in xstatus, LIU Zhiwei, 10:52
- Re: [PATCH v3 20/20] target/riscv: Enable uxl field write, Frédéric Pétrot, 10:18
- Re: [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 09:44
- Re: [PATCH v3 20/20] target/riscv: Enable uxl field write, Richard Henderson, 06:50
- Re: [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN, Richard Henderson, 06:47
- Re: [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE, Richard Henderson, 06:38
- Re: [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN, Richard Henderson, 06:35
- Re: [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE, Richard Henderson, 06:33
- Re: [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE, Richard Henderson, 06:33
- Re: [PATCH v3 12/20] target/riscv: Split out the vill from vtype, Richard Henderson, 06:31
- Re: [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base, Richard Henderson, 06:29
- Re: [PATCH v3 10/20] target/riscv: Calculate address according to XLEN, Richard Henderson, 06:28
- Re: [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base], Richard Henderson, 06:27
- Re: [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN, Richard Henderson, 06:22
- Re: [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write, Richard Henderson, 06:19
- [PATCH v3 20/20] target/riscv: Enable uxl field write, LIU Zhiwei, 01:08
- [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 01:08
- [PATCH v3 18/20] target/riscv: Adjust vector address with mask, LIU Zhiwei, 01:07
- [PATCH v3 17/20] target/riscv: Fix check range for first fault only, LIU Zhiwei, 01:07
- [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 01:06
- [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 01:06
- [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 01:05
- [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 01:04
- [PATCH v3 12/20] target/riscv: Split out the vill from vtype, LIU Zhiwei, 01:04
- [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 01:03
- [PATCH v3 10/20] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 01:03
- [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 01:02
- [PATCH v3 08/20] target/riscv: Create current pm fields in env, LIU Zhiwei, 01:02
- [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 01:01
- [PATCH v3 06/20] target/riscv: Relax debug check for pm write, LIU Zhiwei, 01:01
- [PATCH v3 05/20] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 01:00
- [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 01:00
- [PATCH v3 03/20] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 00:59
- [PATCH v3 02/20] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 00:59
- [PATCH v3 01/20] target/riscv: Don't save pc when exception return, LIU Zhiwei, 00:58
- [PATCH v3 00/20] Support UXL filed in xstatus, LIU Zhiwei, 00:58
- Re: [PATCH v2 05/14] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 00:04
November 10, 2021
- Re: [PATCH v2 14/14] target/riscv: Enable uxl field write, Richard Henderson, 10:02
- Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, Richard Henderson, 10:01
- Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask, Richard Henderson, 09:43
- Re: [PATCH v2 05/14] target/riscv: Calculate address according to XLEN, Richard Henderson, 09:41
- Re: [PATCH v2 14/14] target/riscv: Enable uxl field write, LIU Zhiwei, 09:39
- Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, LIU Zhiwei, 09:27
- Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask, LIU Zhiwei, 09:08
- Re: [PATCH v2 05/14] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 08:45
- Re: [PATCH v2 09/14] target/riscv: Relax debug check for pm write, Richard Henderson, 06:32
- Re: [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN, Richard Henderson, 06:29
- Re: [PATCH v2 14/14] target/riscv: Enable uxl field write, Richard Henderson, 06:27
- Re: [PATCH v2 13/14] target/riscv: Don't save pc when exception return, Richard Henderson, 06:26
- Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, Richard Henderson, 06:23
- Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask, Richard Henderson, 06:11
- Re: [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN, Richard Henderson, 05:55
- Re: [PATCH v2 05/14] target/riscv: Calculate address according to XLEN, Richard Henderson, 05:52
- Re: [PATCH v2 01/14] target/riscv: Sign extend pc for different XLEN, Richard Henderson, 05:19
- Re: [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 04:42
- [PATCH v2 14/14] target/riscv: Enable uxl field write, LIU Zhiwei, 02:12
- [PATCH v2 13/14] target/riscv: Don't save pc when exception return, LIU Zhiwei, 02:11
- [PATCH v2 12/14] target/riscv: Split out the vill from vtype, LIU Zhiwei, 02:11
- [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 02:10
- [PATCH v2 10/14] target/riscv: Adjust vector address with mask, LIU Zhiwei, 02:10
- [PATCH v2 09/14] target/riscv: Relax debug check for pm write, LIU Zhiwei, 02:09
- [PATCH v2 08/14] target/riscv: Fix check range for first fault only, LIU Zhiwei, 02:09
- [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 02:08
- [PATCH v2 06/14] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 02:08
- [PATCH v2 05/14] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 02:07
- [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 02:07
- [PATCH v2 03/14] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 02:06
- [PATCH v2 02/14] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 02:06
- [PATCH v2 01/14] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 02:05
- [PATCH v2 00/14] Support UXL filed in xstatus, LIU Zhiwei, 02:05
November 09, 2021
- Re: [PATCH 13/13] target/riscv: Enable uxl field write, LIU Zhiwei, 22:01
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 04:26
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 04:06
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 03:39
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 03:18
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 03:04
- Re: [PATCH 11/13] target/riscv: Switch context in exception return, LIU Zhiwei, 01:51
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 01:45
- Re: [PATCH 11/13] target/riscv: Switch context in exception return, LIU Zhiwei, 01:38
November 08, 2021
- Re: [PATCH 13/13] target/riscv: Enable uxl field write, LIU Zhiwei, 07:10
- Re: [PATCH 11/13] target/riscv: Switch context in exception return, LIU Zhiwei, 06:23
- Re: [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol, LIU Zhiwei, 04:39
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 04:29
November 04, 2021
- Re: [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR, Bin Meng, 07:49
- Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable, Bin Meng, 07:45
- Re: [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu, Bin Meng, 07:11
- Re: [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for, Bin Meng, 07:08
- Re: [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function, Bin Meng, 07:00
- Re: [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs, Alistair Francis, 00:57
- Re: [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback, Alistair Francis, 00:53
- Re: [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs, Alistair Francis, 00:51
- Re: [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs, Alistair Francis, 00:50
- Re: [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Alistair Francis, 00:43
November 03, 2021
- Re: [PATCH] target/riscv: machine: Sort the .subsections, Alistair Francis, 17:52
- Re: [RFC 3/6] target/riscv: rvk: add flag support for Zk/Zkn/Zknd/Zknd/Zkne/Zknh/Zks/Zksed/Zksh/Zkr, liweiwei, 03:23
- Re: [PATCH v2 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(), Alistair Francis, 02:00
- Re: [PATCH v2 4/7] target/riscv: cpu: Add a config option for native debug, Alistair Francis, 01:59
- Re: [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs, Alistair Francis, 01:57
- Re: [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR, Alistair Francis, 01:51
- Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable, Alistair Francis, 01:51
- Re: [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu, Alistair Francis, 01:48
- Re: [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for, Alistair Francis, 01:43
- Re: [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function, Alistair Francis, 01:40
- Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 01:30
November 02, 2021
- Re: [RFC 3/6] target/riscv: rvk: add flag support for Zk/Zkn/Zknd/Zknd/Zkne/Zknh/Zks/Zksed/Zksh/Zkr, Richard Henderson, 21:22
- Re: [RFC 4/6] target/riscv: rvk: add implementation of instructions for Zk*, liweiwei, 21:08
- Re: [RFC 3/6] target/riscv: rvk: add flag support for Zk/Zkn/Zknd/Zknd/Zkne/Zknh/Zks/Zksed/Zksh/Zkr, liweiwei, 21:06
- Re: [RFC 2/6] target/riscv: rvk: add implementation of instructions for Zbk* - reuse partial instructions of Zbb/Zbc extensions - add brev8 packh, unzip, zip, etc., liweiwei, 20:56
- Re: [RFC 4/6] target/riscv: rvk: add implementation of instructions for Zk*, Richard Henderson, 14:56
- Re: [RFC 3/6] target/riscv: rvk: add flag support for Zk/Zkn/Zknd/Zknd/Zkne/Zknh/Zks/Zksed/Zksh/Zkr, Richard Henderson, 13:56
- Re: [RFC 2/6] target/riscv: rvk: add implementation of instructions for Zbk* - reuse partial instructions of Zbb/Zbc extensions - add brev8 packh, unzip, zip, etc., Richard Henderson, 11:45
- Re: [RFC 1/6] target/riscv: rvk: add flag support for Zbk[bcx], liweiwei, 11:01
- Re: [RFC 1/6] target/riscv: rvk: add flag support for Zbk[bcx], Richard Henderson, 10:18
- Re: [PATCH v5 0/8] target/riscv: support Zfh, Zfhmin extension v0.1, Frank Chang, 10:07
- [RFC 2/6] target/riscv: rvk: add implementation of instructions for Zbk* - reuse partial instructions of Zbb/Zbc extensions - add brev8 packh, unzip, zip, etc., liweiwei, 09:39
- [RFC 6/6] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions, liweiwei, 09:39
- [RFC 1/6] target/riscv: rvk: add flag support for Zbk[bcx], liweiwei, 09:39
- [RFC 5/6] target/riscv: rvk: add CSR support for Zkr: - add SEED CSR - add USEED, SSEED fields for MSECCFG CSR, liweiwei, 09:39
- [RFC 4/6] target/riscv: rvk: add implementation of instructions for Zk*, liweiwei, 09:39
- [RFC 0/6] support subsets of scalar crypto extension, liweiwei, 09:39
- [RFC 3/6] target/riscv: rvk: add flag support for Zk/Zkn/Zknd/Zknd/Zkne/Zknh/Zks/Zksed/Zksh/Zkr, liweiwei, 09:39
- Re: [PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns, Richard Henderson, 09:22
- Re: [PATCH v4 13/17] target/riscv: support for 128-bit M extension, Richard Henderson, 09:05
- Re: [PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions, Richard Henderson, 08:43
- Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs, Bin Meng, 06:52
- Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 06:24
- Re: [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN, Richard Henderson, 06:20
- Re: [PATCH 02/13] target/riscv: Extend pc for runtime pc write, Richard Henderson, 06:18
- Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs, Bin Meng, 02:52
November 01, 2021
- Re: [PATCH 02/13] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 21:48
- Re: [PATCH 13/13] target/riscv: Enable uxl field write, Richard Henderson, 13:01
- Re: [PATCH 12/13] target/riscv: Don't save pc when exception return, Richard Henderson, 12:50
- Re: [PATCH 11/13] target/riscv: Switch context in exception return, Richard Henderson, 12:43
- Re: [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol, Richard Henderson, 12:33
- Re: [PATCH 05/13] target/riscv: Calculate address according to ol, LIU Zhiwei, 11:56
- Re: [PATCH 08/13] target/riscv: Fix check range for first fault only, Richard Henderson, 09:41
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 07:35
- Re: [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol, Richard Henderson, 06:56
- Re: [PATCH 06/13] target/riscv: Adjust vsetvl according to ol, Richard Henderson, 06:53
- Re: [PATCH 05/13] target/riscv: Calculate address according to ol, Richard Henderson, 06:46
- Re: [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen, Richard Henderson, 06:40
- Re: [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN, Richard Henderson, 06:35
- Re: [PATCH 02/13] target/riscv: Extend pc for runtime pc write, Richard Henderson, 06:33
- Re: [PATCH 01/13] target/riscv: Sign extend pc for different ol, Richard Henderson, 06:30
- [PATCH 08/13] target/riscv: Fix check range for first fault only, LIU Zhiwei, 06:02
- [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol, LIU Zhiwei, 06:02
- [PATCH 13/13] target/riscv: Enable uxl field write, LIU Zhiwei, 06:02
- [PATCH 06/13] target/riscv: Adjust vsetvl according to ol, LIU Zhiwei, 06:02
- [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol, LIU Zhiwei, 06:02
- [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 06:02
- [PATCH 12/13] target/riscv: Don't save pc when exception return, LIU Zhiwei, 06:02
- [PATCH 05/13] target/riscv: Calculate address according to ol, LIU Zhiwei, 06:02
- [PATCH 00/13] Support UXL filed in xstatus., LIU Zhiwei, 06:02
- [PATCH 01/13] target/riscv: Sign extend pc for different ol, LIU Zhiwei, 06:02
- [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 06:02
- [PATCH 11/13] target/riscv: Switch context in exception return, LIU Zhiwei, 06:02
- [PATCH 02/13] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 06:02
- [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 06:02
- Re: [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Bin Meng, 04:59
- Re: [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs, Anup Patel, 03:57
- Re: [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs, Alistair Francis, 02:56
- Re: [PATCH] target/riscv: machine: Sort the .subsections, Alistair Francis, 02:53
- Re: [PATCH v9 01/76] target/riscv: drop vector 0.7.1 and add 1.0 support, Bin Meng, 02:45

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