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Re: [PATCH v4 18/20] target/riscv: Adjust vector address with mask
From: |
Alistair Francis |
Subject: |
Re: [PATCH v4 18/20] target/riscv: Adjust vector address with mask |
Date: |
Fri, 19 Nov 2021 22:46:44 +1000 |
On Fri, Nov 12, 2021 at 2:10 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> The mask comes from the pointer masking extension, or the max value
> corresponding to XLEN bits.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/vector_helper.c | 23 ++++++++++++++---------
> 1 file changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 4cd6476b82..d8083dd3a4 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -115,6 +115,11 @@ static inline uint32_t vext_maxsz(uint32_t desc)
> return simd_maxsz(desc) << vext_lmul(desc);
> }
>
> +static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
> +{
> + return (addr & env->cur_pmmask) | env->cur_pmbase;
> +}
> +
> /*
> * This function checks watchpoint before real load operation.
> *
> @@ -132,12 +137,12 @@ static void probe_pages(CPURISCVState *env,
> target_ulong addr,
> target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
> target_ulong curlen = MIN(pagelen, len);
>
> - probe_access(env, addr, curlen, access_type,
> + probe_access(env, adjust_addr(env, addr), curlen, access_type,
> cpu_mmu_index(env, false), ra);
> if (len > curlen) {
> addr += curlen;
> curlen = len - curlen;
> - probe_access(env, addr, curlen, access_type,
> + probe_access(env, adjust_addr(env, addr), curlen, access_type,
> cpu_mmu_index(env, false), ra);
> }
> }
> @@ -298,7 +303,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
> }
> while (k < nf) {
> target_ulong addr = base + stride * i + k * msz;
> - ldst_elem(env, addr, i + k * vlmax, vd, ra);
> + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
> k++;
> }
> }
> @@ -391,7 +396,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState
> *env, uint32_t desc,
> k = 0;
> while (k < nf) {
> target_ulong addr = base + (i * nf + k) * msz;
> - ldst_elem(env, addr, i + k * vlmax, vd, ra);
> + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
> k++;
> }
> }
> @@ -528,7 +533,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
> }
> while (k < nf) {
> abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
> - ldst_elem(env, addr, i + k * vlmax, vd, ra);
> + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
> k++;
> }
> }
> @@ -618,7 +623,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
> if (!vm && !vext_elem_mask(v0, mlen, i)) {
> continue;
> }
> - addr = base + nf * i * msz;
> + addr = adjust_addr(env, base + nf * i * msz);
> if (i == 0) {
> probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
> } else {
> @@ -645,7 +650,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
> break;
> }
> remain -= offset;
> - addr += offset;
> + addr = adjust_addr(env, addr + offset);
> }
> }
> }
> @@ -661,7 +666,7 @@ ProbeSuccess:
> }
> while (k < nf) {
> target_ulong addr = base + (i * nf + k) * msz;
> - ldst_elem(env, addr, i + k * vlmax, vd, ra);
> + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
> k++;
> }
> }
> @@ -800,7 +805,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
> continue;
> }
> addr = get_index_addr(base, i, vs2);
> - noatomic_op(vs3, addr, wd, i, env, ra);
> + noatomic_op(vs3, adjust_addr(env, addr), wd, i, env, ra);
> }
> clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz);
> }
> --
> 2.25.1
>
>
- Re: [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE, (continued)
- [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/11
- [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 17/20] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/11
- [PATCH v4 18/20] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/11
- Re: [PATCH v4 18/20] target/riscv: Adjust vector address with mask,
Alistair Francis <=
- [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 20/20] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/11
- Re: [PATCH v4 00/20] Support UXL filed in xstatus, Alistair Francis, 2021/11/19