Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles

[Philippe Mathieu-Daudé]

Hi Frédéric,

On 11/24/21 07:55, Frédéric Pétrot wrote:
> On 24/11/2021 07:12, Alistair Francis wrote:
>> On Sat, Nov 13, 2021 at 1:16 AM Frédéric Pétrot
>> <frederic.petrot@univ-grenoble-alpes.fr> wrote:
>>>
>>> This patch is kind of a mess because several files have to be slightly
>>> modified to allow for a new target. In the current status, we have done
>>> our best to have RV64 and RV128 under the same RV64 umbrella, but there
>>> is still work to do to have a single executable for both.
>>> In particular, we have no atomic accesses for aligned 128-bit addresses.
>>>
>>> Once this patch applied, adding risc128-sofmmu to --target-list produces
>>> a (no so useful yet) executable.
>>
>> I can't remember if we discussed this before, but do we need the
>> riscv128-sofmmu executable? Can we instead just use a riscv64-sofmmu
>> executable?
> 
>   Hello Alistair,
>   Richard was also advocating for a single executable, but pointed out that
>   we need to disable mttcg because there is a need for specific tcg
> support for
>   128-bit aligned atomics.
>   Given my understanding of that part of QEMU, I choose the easy way to
> disable
>   it once and for all at compile time until we have that.


In rv128_base_cpu_init():

  if (qemu_tcg_mttcg_enabled) {
      /* Missing 128-bit aligned atomics */
      error_report("128-bit RISC-V currently does not work"
                   " with Multi Threaded TCG. Please use:"
                   " -accel tcg,thread=single");
      exit(EXIT_FAILURE);
  }

Regards,

Phil.