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[PATCH v11 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing
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From: |
frank . chang |
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Subject: |
[PATCH v11 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers |
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Date: |
Fri, 10 Dec 2021 15:55:57 +0800 |
From: Frank Chang <frank.chang@sifive.com>
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5d1eec1ea0..3dfbc17738 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -48,6 +48,11 @@ static RISCVException fs(CPURISCVState *env, int csrno)
static RISCVException vs(CPURISCVState *env, int csrno)
{
if (env->misa_ext & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#endif
return RISCV_EXCP_NONE;
}
return RISCV_EXCP_ILLEGAL_INST;
--
2.31.1
- [PATCH v11 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support, (continued)
- [PATCH v11 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/12/10
- [PATCH v11 02/77] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/12/10
- [PATCH v11 03/77] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/12/10
- [PATCH v11 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, frank . chang, 2021/12/10
- [PATCH v11 05/77] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/12/10
- [PATCH v11 06/77] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/12/10
- [PATCH v11 09/77] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/12/10
- [PATCH v11 08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/12/10
- [PATCH v11 10/77] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/12/10
- [PATCH v11 07/77] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/12/10
- [PATCH v11 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers,
frank . chang <=
- [PATCH v11 12/77] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/12/10
- [PATCH v11 13/77] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/12/10
- [PATCH v11 15/77] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/12/10
- [PATCH v11 16/77] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2021/12/10
- [PATCH v11 17/77] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2021/12/10
- [PATCH v11 18/77] target/riscv: rvv-1.0: remove amo operations instructions, frank . chang, 2021/12/10
- [PATCH v11 14/77] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/12/10
- [PATCH v11 19/77] target/riscv: rvv-1.0: configure instructions, frank . chang, 2021/12/10
- [PATCH v11 22/77] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2021/12/10
- [PATCH v11 20/77] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2021/12/10