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qemu-riscv (thread)
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Last Modified: Fri Dec 31 2021 15:09:02 -0500
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[PATCH v2 0/3] support subsets of virtual memory extension
,
Weiwei Li
,
2021/12/31
[PATCH v2 1/3] target/riscv: add support for svnapot extension
,
Weiwei Li
,
2021/12/31
[PATCH v2 3/3] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
2021/12/31
[PATCH v2 2/3] target/riscv: add support for svinval extension
,
Weiwei Li
,
2021/12/31
[PATCH v2 0/6] support subsets of Float-Point in Integer Registers extensions
,
Weiwei Li
,
2021/12/30
[PATCH v2 5/6] target/riscv: add support for zhinx/zhinxmin
,
Weiwei Li
,
2021/12/30
Re: [PATCH v2 5/6] target/riscv: add support for zhinx/zhinxmin
,
Richard Henderson
,
2021/12/31
[PATCH v2 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Weiwei Li
,
2021/12/30
Re: [PATCH v2 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Bin Meng
,
2021/12/31
[PATCH v2 4/6] target/riscv: add support for zdinx
,
Weiwei Li
,
2021/12/30
Re: [PATCH v2 4/6] target/riscv: add support for zdinx
,
Richard Henderson
,
2021/12/31
[PATCH v2 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
2021/12/30
Re: [PATCH v2 3/6] target/riscv: add support for zfinx
,
Richard Henderson
,
2021/12/31
Re: [PATCH v2 3/6] target/riscv: add support for zfinx
,
Richard Henderson
,
2021/12/31
[PATCH v2 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
,
Weiwei Li
,
2021/12/30
[PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
2021/12/30
Re: [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Richard Henderson
,
2021/12/31
[PATCH v3 0/7] support subsets of scalar crypto extension
,
liweiwei
,
2021/12/30
[PATCH v3 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*
,
liweiwei
,
2021/12/30
Re: [PATCH v3 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*
,
Bin Meng
,
2021/12/30
Re: [PATCH v3 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*
,
liweiwei
,
2021/12/30
[PATCH v3 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
,
liweiwei
,
2021/12/30
Re: [PATCH v3 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
,
Philippe Mathieu-Daudé
,
2021/12/30
Re: [PATCH v3 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
,
liweiwei
,
2021/12/30
[PATCH v3 6/7] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
,
liweiwei
,
2021/12/30
[PATCH v3 5/7] target/riscv: rvk: add CSR support for Zkr
,
liweiwei
,
2021/12/30
[PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties
,
liweiwei
,
2021/12/30
[PATCH v3 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
,
liweiwei
,
2021/12/30
[PATCH v3 4/7] target/riscv: rvk: add implementation of instructions for Zk*
,
liweiwei
,
2021/12/30
[PATCH v6 00/23] QEMU RISC-V AIA support
,
Anup Patel
,
2021/12/30
[PATCH v6 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
,
Anup Patel
,
2021/12/30
[PATCH v6 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs
,
Anup Patel
,
2021/12/30
[PATCH v6 03/23] target/riscv: Implement hgeie and hgeip CSRs
,
Anup Patel
,
2021/12/30
[PATCH v6 04/23] target/riscv: Improve delivery of guest external interrupts
,
Anup Patel
,
2021/12/30
[PATCH v6 05/23] target/riscv: Allow setting CPU feature from machine/device emulation
,
Anup Patel
,
2021/12/30
[PATCH v6 06/23] target/riscv: Add AIA cpu feature
,
Anup Patel
,
2021/12/30
[PATCH v6 07/23] target/riscv: Add defines for AIA CSRs
,
Anup Patel
,
2021/12/30
[PATCH v6 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Anup Patel
,
2021/12/30
[PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
2021/12/30
[PATCH v6 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Anup Patel
,
2021/12/30
[PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Anup Patel
,
2021/12/30
[PATCH v6 12/23] target/riscv: Implement AIA interrupt filtering CSRs
,
Anup Patel
,
2021/12/30
[PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Anup Patel
,
2021/12/30
[PATCH v6 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
,
Anup Patel
,
2021/12/30
[PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Anup Patel
,
2021/12/30
[PATCH v6 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
,
Anup Patel
,
2021/12/30
[PATCH v6 17/23] target/riscv: Allow users to force enable AIA CSRs in HART
,
Anup Patel
,
2021/12/30
[PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
2021/12/30
[PATCH v6 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine
,
Anup Patel
,
2021/12/30
[PATCH v6 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
2021/12/30
[PATCH v6 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
,
Anup Patel
,
2021/12/30
[PATCH v6 22/23] docs/system: riscv: Document AIA options for virt machine
,
Anup Patel
,
2021/12/30
[PATCH v6 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
,
Anup Patel
,
2021/12/30
[PATCH 00/17] Add RISC-V RVV Zve32f and Zve64f extensions
,
frank . chang
,
2021/12/28
[PATCH 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
,
frank . chang
,
2021/12/28
[PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns
,
frank . chang
,
2021/12/28
[PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
,
frank . chang
,
2021/12/28
[PATCH 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
,
frank . chang
,
2021/12/28
[PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
,
frank . chang
,
2021/12/28
[PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
,
frank . chang
,
2021/12/28
[PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
,
frank . chang
,
2021/12/28
[PATCH 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
,
frank . chang
,
2021/12/28
[PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
,
frank . chang
,
2021/12/28
[PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
,
frank . chang
,
2021/12/28
[PATCH 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
,
frank . chang
,
2021/12/28
[PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns
,
frank . chang
,
2021/12/28
[PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
,
frank . chang
,
2021/12/28
[PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
,
frank . chang
,
2021/12/28
[PATCH 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
,
frank . chang
,
2021/12/28
[PATCH 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
,
frank . chang
,
2021/12/28
[PATCH 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
,
frank . chang
,
2021/12/28
[PATCH 0/3] Fix RVV calling incorrect RFV/RVD check functions bug
,
frank . chang
,
2021/12/28
[PATCH 2/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check funtion for widening fp/int type-convert insns
,
frank . chang
,
2021/12/28
[PATCH 1/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check funtion for widening fp insns
,
frank . chang
,
2021/12/28
[PATCH 3/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check funtion for narrowing fp/int type-convert insns
,
frank . chang
,
2021/12/28
Re: [PATCH 0/3] Fix RVV calling incorrect RFV/RVD check functions bug
,
Frank Chang
,
2021/12/28
Re: [PATCH 0/3] Fix RVV calling incorrect RFV/RVD check functions bug
,
Frank Chang
,
2021/12/30
[PATCH 0/2] Align SiFive PDMA behavior to real hardware
,
Jim Shu
,
2021/12/27
[PATCH 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
,
Jim Shu
,
2021/12/27
Re: [PATCH 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
,
Philippe Mathieu-Daudé
,
2021/12/28
[PATCH 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
,
Jim Shu
,
2021/12/27
Re: [PATCH 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
,
Philippe Mathieu-Daudé
,
2021/12/28
Re: [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support
,
Frank Chang
,
2021/12/26
[PATCH 0/6] support subsets of Float-Point in Integer Registers extensions
,
liweiwei
,
2021/12/23
[PATCH 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
liweiwei
,
2021/12/23
Re: [PATCH 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Richard Henderson
,
2021/12/24
[PATCH 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
,
liweiwei
,
2021/12/23
Re: [PATCH 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
,
Richard Henderson
,
2021/12/24
[PATCH 5/6] target/riscv: add support for zhinx/zhinxmin
,
liweiwei
,
2021/12/23
Re: [PATCH 5/6] target/riscv: add support for zhinx/zhinxmin
,
Richard Henderson
,
2021/12/24
Re: [PATCH 5/6] target/riscv: add support for zhinx/zhinxmin
,
liweiwei
,
2021/12/24
[PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx
,
liweiwei
,
2021/12/23
Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx
,
Richard Henderson
,
2021/12/24
Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx
,
liweiwei
,
2021/12/24
Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx
,
Richard Henderson
,
2021/12/25
Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx
,
liweiwei
,
2021/12/25
Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx
,
liweiwei
,
2021/12/25
Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx
,
Richard Henderson
,
2021/12/25
[PATCH 3/6] target/riscv: add support for zfinx
,
liweiwei
,
2021/12/23
Re: [PATCH 3/6] target/riscv: add support for zfinx
,
Richard Henderson
,
2021/12/24
Re: [PATCH 3/6] target/riscv: add support for zfinx
,
liweiwei
,
2021/12/24
[PATCH 4/6] target/riscv: add support for zdinx
,
liweiwei
,
2021/12/23
Re: [PATCH 4/6] target/riscv: add support for zdinx
,
Richard Henderson
,
2021/12/24
Re: [PATCH 4/6] target/riscv: add support for zdinx
,
liweiwei
,
2021/12/24
[PATCH] target/riscv: make H-extension non-experimental
,
Vineet Gupta
,
2021/12/21
Re: [PATCH] target/riscv: make H-extension non-experimental
,
Alistair Francis
,
2021/12/21
[PATCH v3 00/12] Add riscv kvm accel support
,
Yifei Jiang
,
2021/12/20
[PATCH v3 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Yifei Jiang
,
2021/12/20
Re: [PATCH v3 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Anup Patel
,
2021/12/23
[PATCH v3 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Yifei Jiang
,
2021/12/20
[PATCH v3 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Yifei Jiang
,
2021/12/20
[PATCH v3 03/12] target/riscv: Implement function kvm_arch_init_vcpu
,
Yifei Jiang
,
2021/12/20
[PATCH v3 07/12] target/riscv: Support setting external interrupt by KVM
,
Yifei Jiang
,
2021/12/20
Re: [PATCH v3 07/12] target/riscv: Support setting external interrupt by KVM
,
Anup Patel
,
2021/12/23
[PATCH v3 05/12] target/riscv: Implement kvm_arch_put_registers
,
Yifei Jiang
,
2021/12/20
[PATCH v3 09/12] target/riscv: Add host cpu type
,
Yifei Jiang
,
2021/12/20
[PATCH v3 12/12] target/riscv: Support virtual time context synchronization
,
Yifei Jiang
,
2021/12/20
[PATCH v3 11/12] target/riscv: Implement virtual time adjusting with vm state changing
,
Yifei Jiang
,
2021/12/20
[PATCH v3 01/12] update-linux-headers: Add asm-riscv/kvm.h
,
Yifei Jiang
,
2021/12/20
[PATCH v3 04/12] target/riscv: Implement kvm_arch_get_registers
,
Yifei Jiang
,
2021/12/20
[PATCH v3 06/12] target/riscv: Support start kernel directly by KVM
,
Yifei Jiang
,
2021/12/20
Re: [PATCH v3 06/12] target/riscv: Support start kernel directly by KVM
,
Anup Patel
,
2021/12/23
Re: [PATCH v3 06/12] target/riscv: Support start kernel directly by KVM
,
Anup Patel
,
2021/12/23
[PATCH v4 0/3] RISC-V: Populate mtval and stval
,
Alistair Francis
,
2021/12/20
[PATCH v4 1/3] target/riscv: Set the opcode in DisasContext
,
Alistair Francis
,
2021/12/20
Re: [PATCH v4 1/3] target/riscv: Set the opcode in DisasContext
,
Bin Meng
,
2021/12/21
[PATCH v4 2/3] target/riscv: Fixup setting GVA
,
Alistair Francis
,
2021/12/20
Re: [PATCH v4 2/3] target/riscv: Fixup setting GVA
,
Richard Henderson
,
2021/12/20
Re: [PATCH v4 2/3] target/riscv: Fixup setting GVA
,
Bin Meng
,
2021/12/21
[PATCH v4 3/3] target/riscv: Implement the stval/mtval illegal instruction
,
Alistair Francis
,
2021/12/20
Re: [PATCH v4 3/3] target/riscv: Implement the stval/mtval illegal instruction
,
Richard Henderson
,
2021/12/20
Re: [PATCH v4 3/3] target/riscv: Implement the stval/mtval illegal instruction
,
Bin Meng
,
2021/12/21
[PATCH v4 1/1] target/riscv: Fix PMP propagation for tlb
,
LIU Zhiwei
,
2021/12/16
[PATCH] target/riscv: Enable bitmanip Zb[abcs] instructions
,
Vineet Gupta
,
2021/12/16
Re: [PATCH] target/riscv: Enable bitmanip Zb[abcs] instructions
,
Alistair Francis
,
2021/12/16
Re: [PATCH] target/riscv: Enable bitmanip Zb[abcs] instructions
,
Alistair Francis
,
2021/12/17
[PATCH v2 0/9] A collection of RISC-V cleanups and improvements
,
Alistair Francis
,
2021/12/15
[PATCH v2 1/9] hw/intc: sifive_plic: Add a reset function
,
Alistair Francis
,
2021/12/15
Re: [PATCH v2 1/9] hw/intc: sifive_plic: Add a reset function
,
Philippe Mathieu-Daudé
,
2021/12/16
Re: [PATCH v2 1/9] hw/intc: sifive_plic: Add a reset function
,
Bin Meng
,
2021/12/21
[PATCH v2 2/9] hw/intc: sifive_plic: Cleanup the write function
,
Alistair Francis
,
2021/12/15
[PATCH v2 3/9] hw/intc: sifive_plic: Cleanup the read function
,
Alistair Francis
,
2021/12/15
[PATCH v2 4/9] hw/intc: sifive_plic: Cleanup remaining functions
,
Alistair Francis
,
2021/12/15
Re: [PATCH v2 4/9] hw/intc: sifive_plic: Cleanup remaining functions
,
Bin Meng
,
2021/12/21
[PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental
,
Alistair Francis
,
2021/12/15
Re: [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental
,
Anup Patel
,
2021/12/16
Re: [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental
,
Bin Meng
,
2021/12/19
[PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default
,
Alistair Francis
,
2021/12/15
Re: [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default
,
Anup Patel
,
2021/12/16
Re: [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default
,
Bin Meng
,
2021/12/19
[PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation
,
Alistair Francis
,
2021/12/15
Re: [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation
,
Bin Meng
,
2021/12/20
[PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores
,
Alistair Francis
,
2021/12/15
Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores
,
Anup Patel
,
2021/12/16
Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores
,
Philippe Mathieu-Daudé
,
2021/12/16
Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores
,
Alistair Francis
,
2021/12/20
Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores
,
Bin Meng
,
2021/12/20
[PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency
,
Alistair Francis
,
2021/12/15
Re: [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency
,
Anup Patel
,
2021/12/16
Re: [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency
,
Bin Meng
,
2021/12/20
Re: [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency
,
Alistair Francis
,
2021/12/21
Re: [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency
,
Bin Meng
,
2021/12/21
[PATCH] riscv: Set 5.4 as minimum kernel version for riscv32
,
Khem Raj
,
2021/12/15
Re: [PATCH] riscv: Set 5.4 as minimum kernel version for riscv32
,
Palmer Dabbelt
,
2021/12/15
Re: [PATCH] riscv: Set 5.4 as minimum kernel version for riscv32
,
Alistair Francis
,
2021/12/16
Re: [PATCH] riscv: Set 5.4 as minimum kernel version for riscv32
,
Khem Raj
,
2021/12/16
[PULL 01/13] hw/sd/ssi-sd: Do not create SD card within controller's realize
,
Markus Armbruster
,
2021/12/15
[PULL 02/13] hw: Replace trivial drive_get_next() by drive_get()
,
Markus Armbruster
,
2021/12/15
Re: [RFC PATCH 1/3] target/riscv: add support for svnapot extension
,
Alistair Francis
,
2021/12/14
Re: [RFC PATCH 3/3] target/riscv: add support for svpbmt extension
,
Heiko Stuebner
,
2021/12/14
[PATCH] target/riscv/pmp: fix no pmp illegal intrs
,
Nikita Shubin
,
2021/12/14
Re: [PATCH] target/riscv/pmp: fix no pmp illegal intrs
,
Richard Henderson
,
2021/12/14
Re: [PATCH] target/riscv/pmp: fix no pmp illegal intrs
,
Richard Henderson
,
2021/12/14
Re: [PATCH] target/riscv/pmp: fix no pmp illegal intrs
,
Nikita Shubin
,
2021/12/15
Re: [PATCH] target/riscv/pmp: fix no pmp illegal intrs
,
Alistair Francis
,
2021/12/21
[PATCH] target/riscv/pmp: fix no pmp illegal intrs
,
Nikita Shubin
,
2021/12/21
Re: [PATCH] target/riscv/pmp: fix no pmp illegal intrs
,
Alistair Francis
,
2021/12/22
[PATCH] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr
,
Jessica Clarke
,
2021/12/13
Re: [PATCH] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr
,
Alistair Francis
,
2021/12/17
Re: [PATCH] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr
,
Alistair Francis
,
2021/12/17
[PATCH v7 00/18] Adding partial support for 128-bit riscv target
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 04/18] target/riscv: additional macros to check instruction support
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 02/18] exec/memop: Adding signed quad and octo defines
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 03/18] qemu/int128: addition of div/rem 128-bit operations
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 05/18] target/riscv: separation of bitwise logic and arithmetic helpers
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 01/18] exec/memop: Adding signedness to quad definitions
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 06/18] target/riscv: array for the 64 upper bits of 128-bit registers
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 09/18] target/riscv: accessors to registers upper part and 128-bit load/store
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 17/18] target/riscv: modification of the trans_csrxx for 128-bit support
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 13/18] target/riscv: support for 128-bit arithmetic instructions
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 15/18] target/riscv: adding high part of some csrs
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 08/18] target/riscv: moving some insns close to similar insns
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 12/18] target/riscv: support for 128-bit shift instructions
,
Frédéric Pétrot
,
2021/12/13
Re: [PATCH v7 12/18] target/riscv: support for 128-bit shift instructions
,
Alistair Francis
,
2021/12/21
[PATCH v7 18/18] target/riscv: actual functions to realize crs 128-bit insns
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 10/18] target/riscv: support for 128-bit bitwise instructions
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 14/18] target/riscv: support for 128-bit M extension
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 11/18] target/riscv: support for 128-bit U-type instructions
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Frédéric Pétrot
,
2021/12/13
[PATCH v7 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns
,
Frédéric Pétrot
,
2021/12/13
[PATCH v5 00/23] QEMU RISC-V AIA support
,
Anup Patel
,
2021/12/10
[PATCH v5 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
,
Anup Patel
,
2021/12/10
[PATCH v5 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs
,
Anup Patel
,
2021/12/10
[PATCH v5 03/23] target/riscv: Implement hgeie and hgeip CSRs
,
Anup Patel
,
2021/12/10
[PATCH v5 04/23] target/riscv: Improve delivery of guest external interrupts
,
Anup Patel
,
2021/12/10
[PATCH v5 05/23] target/riscv: Allow setting CPU feature from machine/device emulation
,
Anup Patel
,
2021/12/10
[PATCH v5 06/23] target/riscv: Add AIA cpu feature
,
Anup Patel
,
2021/12/10
[PATCH v5 07/23] target/riscv: Add defines for AIA CSRs
,
Anup Patel
,
2021/12/10
Re: [PATCH v5 07/23] target/riscv: Add defines for AIA CSRs
,
Alistair Francis
,
2021/12/16
[PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Anup Patel
,
2021/12/10
Re: [PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Alistair Francis
,
2021/12/16
[PATCH v5 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
2021/12/10
Re: [PATCH v5 09/23] target/riscv: Implement AIA local interrupt priorities
,
Alistair Francis
,
2021/12/16
[PATCH v5 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Anup Patel
,
2021/12/10
Re: [PATCH v5 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Alistair Francis
,
2021/12/17
[PATCH v5 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Anup Patel
,
2021/12/10
Re: [PATCH v5 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Alistair Francis
,
2021/12/16
[PATCH v5 12/23] target/riscv: Implement AIA interrupt filtering CSRs
,
Anup Patel
,
2021/12/10
[PATCH v5 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Anup Patel
,
2021/12/10
Re: [PATCH v5 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Alistair Francis
,
2021/12/21
Re: [PATCH v5 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Anup Patel
,
2021/12/22
[PATCH v5 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
,
Anup Patel
,
2021/12/10
[PATCH v5 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
,
Anup Patel
,
2021/12/10
Re: [PATCH v5 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
,
Kip Walker
,
2021/12/14
Re: [PATCH v5 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
,
Anup Patel
,
2021/12/15
[PATCH v5 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Anup Patel
,
2021/12/10
[PATCH v5 17/23] target/riscv: Allow users to force enable AIA CSRs in HART
,
Anup Patel
,
2021/12/10
[PATCH v5 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
2021/12/10
[PATCH v5 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine
,
Anup Patel
,
2021/12/10
[PATCH v5 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
2021/12/10
[PATCH v5 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
,
Anup Patel
,
2021/12/10
[PATCH v5 22/23] docs/system: riscv: Document AIA options for virt machine
,
Anup Patel
,
2021/12/10
[PATCH v5 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
,
Anup Patel
,
2021/12/10
[PATCH v2 00/12] Add riscv kvm accel support
,
Yifei Jiang
,
2021/12/10
[PATCH v2 01/12] update-linux-headers: Add asm-riscv/kvm.h
,
Yifei Jiang
,
2021/12/10
[PATCH v2 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Yifei Jiang
,
2021/12/10
[PATCH v2 03/12] target/riscv: Implement function kvm_arch_init_vcpu
,
Yifei Jiang
,
2021/12/10
Re: [PATCH v2 03/12] target/riscv: Implement function kvm_arch_init_vcpu
,
Anup Patel
,
2021/12/12
[PATCH v2 05/12] target/riscv: Implement kvm_arch_put_registers
,
Yifei Jiang
,
2021/12/10
Re: [PATCH v2 05/12] target/riscv: Implement kvm_arch_put_registers
,
Anup Patel
,
2021/12/12
[PATCH v2 04/12] target/riscv: Implement kvm_arch_get_registers
,
Yifei Jiang
,
2021/12/10
Re: [PATCH v2 04/12] target/riscv: Implement kvm_arch_get_registers
,
Anup Patel
,
2021/12/12
[PATCH v2 06/12] target/riscv: Support start kernel directly by KVM
,
Yifei Jiang
,
2021/12/10
Re: [PATCH v2 06/12] target/riscv: Support start kernel directly by KVM
,
Anup Patel
,
2021/12/12
RE: [PATCH v2 06/12] target/riscv: Support start kernel directly by KVM
,
Jiangyifei
,
2021/12/20
[PATCH v2 07/12] target/riscv: Support setting external interrupt by KVM
,
Yifei Jiang
,
2021/12/10
Re: [PATCH v2 07/12] target/riscv: Support setting external interrupt by KVM
,
Anup Patel
,
2021/12/12
RE: [PATCH v2 07/12] target/riscv: Support setting external interrupt by KVM
,
Jiangyifei
,
2021/12/20
[PATCH v2 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Yifei Jiang
,
2021/12/10
Re: [PATCH v2 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Anup Patel
,
2021/12/12
[PATCH v2 09/12] target/riscv: Add host cpu type
,
Yifei Jiang
,
2021/12/10
[PATCH v2 11/12] target/riscv: Implement virtual time adjusting with vm state changing
,
Yifei Jiang
,
2021/12/10
Re: [PATCH v2 11/12] target/riscv: Implement virtual time adjusting with vm state changing
,
Anup Patel
,
2021/12/12
[PATCH v2 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Yifei Jiang
,
2021/12/10
Re: [PATCH v2 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Anup Patel
,
2021/12/13
Re: [PATCH v2 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Richard Henderson
,
2021/12/13
RE: [PATCH v2 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Jiangyifei
,
2021/12/20
[PATCH v2 12/12] target/riscv: Support virtual time context synchronization
,
Yifei Jiang
,
2021/12/10
Re: [PATCH v2 12/12] target/riscv: Support virtual time context synchronization
,
Anup Patel
,
2021/12/12
Re: [PATCH v2 12/12] target/riscv: Support virtual time context synchronization
,
Richard Henderson
,
2021/12/13
RE: [PATCH v2 12/12] target/riscv: Support virtual time context synchronization
,
Jiangyifei
,
2021/12/20
RE: [PATCH v1 12/12] target/riscv: Support virtual time context synchronization
,
Jiangyifei
,
2021/12/10
Re: [PATCH v1 12/12] target/riscv: Support virtual time context synchronization
,
Paolo Bonzini
,
2021/12/10
RE: [PATCH v1 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Jiangyifei
,
2021/12/10
RE: [PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu
,
Jiangyifei
,
2021/12/10
[PATCH v11 00/77] support vector extension v1.0
,
frank . chang
,
2021/12/10
[PATCH v11 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support
,
frank . chang
,
2021/12/10
[PATCH v11 02/77] target/riscv: Use FIELD_EX32() to extract wd field
,
frank . chang
,
2021/12/10
[PATCH v11 03/77] target/riscv: rvv-1.0: add mstatus VS field
,
frank . chang
,
2021/12/10
[PATCH v11 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
,
frank . chang
,
2021/12/10
[PATCH v11 05/77] target/riscv: rvv-1.0: add sstatus VS field
,
frank . chang
,
2021/12/10
[PATCH v11 06/77] target/riscv: rvv-1.0: introduce writable misa.v field
,
frank . chang
,
2021/12/10
[PATCH v11 09/77] target/riscv: rvv-1.0: add vcsr register
,
frank . chang
,
2021/12/10
[PATCH v11 08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
,
frank . chang
,
2021/12/10
[PATCH v11 10/77] target/riscv: rvv-1.0: add vlenb register
,
frank . chang
,
2021/12/10
[PATCH v11 07/77] target/riscv: rvv-1.0: add translation-time vector context status
,
frank . chang
,
2021/12/10
[PATCH v11 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
,
frank . chang
,
2021/12/10
[PATCH v11 12/77] target/riscv: rvv-1.0: remove MLEN calculations
,
frank . chang
,
2021/12/10
[PATCH v11 13/77] target/riscv: rvv-1.0: add fractional LMUL
,
frank . chang
,
2021/12/10
[PATCH v11 15/77] target/riscv: rvv-1.0: update check functions
,
frank . chang
,
2021/12/10
[PATCH v11 16/77] target/riscv: introduce more imm value modes in translator functions
,
frank . chang
,
2021/12/10
[PATCH v11 17/77] target/riscv: rvv:1.0: add translation-time nan-box helper function
,
frank . chang
,
2021/12/10
[PATCH v11 18/77] target/riscv: rvv-1.0: remove amo operations instructions
,
frank . chang
,
2021/12/10
[PATCH v11 14/77] target/riscv: rvv-1.0: add VMA and VTA
,
frank . chang
,
2021/12/10
[PATCH v11 19/77] target/riscv: rvv-1.0: configure instructions
,
frank . chang
,
2021/12/10
[PATCH v11 22/77] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
,
frank . chang
,
2021/12/10
[PATCH v11 20/77] target/riscv: rvv-1.0: stride load and store instructions
,
frank . chang
,
2021/12/10
[PATCH v11 23/77] target/riscv: rvv-1.0: fault-only-first unit stride load
,
frank . chang
,
2021/12/10
[PATCH v11 21/77] target/riscv: rvv-1.0: index load and store instructions
,
frank . chang
,
2021/12/10
[PATCH v11 24/77] target/riscv: rvv-1.0: load/store whole register instructions
,
frank . chang
,
2021/12/10
[PATCH v11 25/77] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
,
frank . chang
,
2021/12/10
[PATCH v11 26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
,
frank . chang
,
2021/12/10
[PATCH v11 28/77] target/riscv: rvv-1.0: floating-point classify instructions
,
frank . chang
,
2021/12/10
[PATCH v11 27/77] target/riscv: rvv-1.0: floating-point square-root instruction
,
frank . chang
,
2021/12/10
[PATCH v11 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction
,
frank . chang
,
2021/12/10
[PATCH v11 29/77] target/riscv: rvv-1.0: count population in mask instruction
,
frank . chang
,
2021/12/10
[PATCH v11 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions
,
frank . chang
,
2021/12/10
[PATCH v11 33/77] target/riscv: rvv-1.0: element index instruction
,
frank . chang
,
2021/12/10
[PATCH v11 34/77] target/riscv: rvv-1.0: allow load element with sign-extended
,
frank . chang
,
2021/12/10
[PATCH v11 32/77] target/riscv: rvv-1.0: iota instruction
,
frank . chang
,
2021/12/10
[PATCH v11 35/77] target/riscv: rvv-1.0: register gather instructions
,
frank . chang
,
2021/12/10
[PATCH v11 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
,
frank . chang
,
2021/12/10
[PATCH v11 40/77] target/riscv: rvv-1.0: integer extension instructions
,
frank . chang
,
2021/12/10
[PATCH v11 36/77] target/riscv: rvv-1.0: integer scalar move instructions
,
frank . chang
,
2021/12/10
[PATCH v11 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions
,
frank . chang
,
2021/12/10
[PATCH v11 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions
,
frank . chang
,
2021/12/10
[PATCH v11 47/77] target/riscv: rvv-1.0: integer comparison instructions
,
frank . chang
,
2021/12/10
[PATCH v11 42/77] target/riscv: rvv-1.0: single-width bit shift instructions
,
frank . chang
,
2021/12/10
[PATCH v11 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
,
frank . chang
,
2021/12/10
[PATCH v11 37/77] target/riscv: rvv-1.0: floating-point move instruction
,
frank . chang
,
2021/12/10
[PATCH v11 39/77] target/riscv: rvv-1.0: whole register move instructions
,
frank . chang
,
2021/12/10
[PATCH v11 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions
,
frank . chang
,
2021/12/10
[PATCH v11 50/77] target/riscv: rvv-1.0: slide instructions
,
frank . chang
,
2021/12/10
[PATCH v11 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
,
frank . chang
,
2021/12/10
[PATCH v11 51/77] target/riscv: rvv-1.0: floating-point slide instructions
,
frank . chang
,
2021/12/10
[PATCH v11 48/77] target/riscv: rvv-1.0: floating-point compare instructions
,
frank . chang
,
2021/12/10
[PATCH v11 49/77] target/riscv: rvv-1.0: mask-register logical instructions
,
frank . chang
,
2021/12/10
[PATCH v11 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
,
frank . chang
,
2021/12/10
[PATCH v11 53/77] target/riscv: rvv-1.0: single-width floating-point reduction
,
frank . chang
,
2021/12/10
[PATCH v11 54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions
,
frank . chang
,
2021/12/10
[PATCH v11 55/77] target/riscv: rvv-1.0: single-width scaling shift instructions
,
frank . chang
,
2021/12/10
[PATCH v11 56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
,
frank . chang
,
2021/12/10
[PATCH v11 57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
,
frank . chang
,
2021/12/10
[PATCH v11 58/77] target/riscv: rvv-1.0: remove integer extract instruction
,
frank . chang
,
2021/12/10
[PATCH v11 59/77] target/riscv: rvv-1.0: floating-point min/max instructions
,
frank . chang
,
2021/12/10
[PATCH v11 60/77] target/riscv: introduce floating-point rounding mode enum
,
frank . chang
,
2021/12/10
[PATCH v11 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
,
frank . chang
,
2021/12/10
[PATCH v11 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert
,
frank . chang
,
2021/12/10
[PATCH v11 63/77] target/riscv: add "set round to odd" rounding mode helper function
,
frank . chang
,
2021/12/10
[PATCH v11 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
,
frank . chang
,
2021/12/10
[PATCH v11 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
,
frank . chang
,
2021/12/10
[PATCH v11 66/77] target/riscv: rvv-1.0: implement vstart CSR
,
frank . chang
,
2021/12/10
[PATCH v11 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
,
frank . chang
,
2021/12/10
[PATCH v11 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
,
frank . chang
,
2021/12/10
[PATCH v11 68/77] target/riscv: gdb: support vector registers for rv64 & rv32
,
frank . chang
,
2021/12/10
[PATCH v11 70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
,
frank . chang
,
2021/12/10
[PATCH v11 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
,
frank . chang
,
2021/12/10
[PATCH v11 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
,
frank . chang
,
2021/12/10
[PATCH v11 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
,
frank . chang
,
2021/12/10
[PATCH v11 72/77] target/riscv: rvv-1.0: add vsetivli instruction
,
frank . chang
,
2021/12/10
[PATCH v11 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
,
frank . chang
,
2021/12/10
[PATCH v11 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment
,
frank . chang
,
2021/12/10
[PATCH v11 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
,
frank . chang
,
2021/12/10
Re: [PATCH v11 00/77] support vector extension v1.0
,
Alistair Francis
,
2021/12/16
[PATCH v6 0/8] target/riscv: support Zfh, Zfhmin extension v0.1
,
frank . chang
,
2021/12/10
[PATCH v6 1/8] target/riscv: zfh: half-precision load and store
,
frank . chang
,
2021/12/10
[PATCH v6 2/8] target/riscv: zfh: half-precision computational
,
frank . chang
,
2021/12/10
[PATCH v6 3/8] target/riscv: zfh: half-precision convert and move
,
frank . chang
,
2021/12/10
[PATCH v6 4/8] target/riscv: zfh: half-precision floating-point compare
,
frank . chang
,
2021/12/10
[PATCH v6 6/8] target/riscv: zfh: add Zfh cpu property
,
frank . chang
,
2021/12/10
[PATCH v6 5/8] target/riscv: zfh: half-precision floating-point classify
,
frank . chang
,
2021/12/10
[PATCH v6 8/8] target/riscv: zfh: add Zfhmin cpu property
,
frank . chang
,
2021/12/10
[PATCH v6 7/8] target/riscv: zfh: implement zfhmin extension
,
frank . chang
,
2021/12/10
Re: [PATCH v6 0/8] target/riscv: support Zfh, Zfhmin extension v0.1
,
Alistair Francis
,
2021/12/14
[PATCH 0/2] RISC-V: Populate mtval and stval
,
Alistair Francis
,
2021/12/10
[PATCH 1/2] target/riscv: Set the opcode in DisasContext
,
Alistair Francis
,
2021/12/10
Re: [PATCH 1/2] target/riscv: Set the opcode in DisasContext
,
Richard Henderson
,
2021/12/10
[PATCH 2/2] target/riscv: Implement the stval/mtval illegal instruction
,
Alistair Francis
,
2021/12/10
Re: [PATCH 2/2] target/riscv: Implement the stval/mtval illegal instruction
,
Richard Henderson
,
2021/12/10
Re: [PATCH v6 09/18] target/riscv: accessors to registers upper part and 128-bit load/store
,
Alistair Francis
,
2021/12/09
Re: [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs
,
Anup Patel
,
2021/12/09
Re: [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Anup Patel
,
2021/12/09
Re: [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Anup Patel
,
2021/12/09
Re: [PATCH v6 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Alistair Francis
,
2021/12/08
Re: [PATCH v6 01/18] exec/memop: Adding signedness to quad definitions
,
Alistair Francis
,
2021/12/08
[PATCH 0/7] A collection of RISC-V cleanups and improvements
,
Alistair Francis
,
2021/12/08
[PATCH 2/7] hw/intc: sifive_plic: Cleanup the write function
,
Alistair Francis
,
2021/12/08
Re: [PATCH 2/7] hw/intc: sifive_plic: Cleanup the write function
,
Richard Henderson
,
2021/12/08
[PATCH 1/7] hw/intc: sifive_plic: Add a reset function
,
Alistair Francis
,
2021/12/08
Re: [PATCH 1/7] hw/intc: sifive_plic: Add a reset function
,
Philippe Mathieu-Daudé
,
2021/12/08
Re: [PATCH 1/7] hw/intc: sifive_plic: Add a reset function
,
Alistair Francis
,
2021/12/09
[PATCH 3/7] hw/intc: sifive_plic: Cleanup the read function
,
Alistair Francis
,
2021/12/08
[PATCH 4/7] hw/intc: sifive_plic: Cleanup remaining functions
,
Alistair Francis
,
2021/12/08
[PATCH 5/7] target/riscv: Mark the Hypervisor extension as non experimental
,
Alistair Francis
,
2021/12/08
[PATCH 6/7] target/riscv: Enable the Hypervisor extension by default
,
Alistair Francis
,
2021/12/08
[PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation
,
Alistair Francis
,
2021/12/08
Re: [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation
,
Philippe Mathieu-Daudé
,
2021/12/08
Re: [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation
,
Markus Armbruster
,
2021/12/10
Re: [PATCH v10 00/77] support vector extension v1.0
,
Alistair Francis
,
2021/12/08
Re: [PATCH v10 00/77] support vector extension v1.0
,
Frank Chang
,
2021/12/10
Re: [PATCH v10 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
,
Alistair Francis
,
2021/12/07
Re: [PATCH v10 70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
,
Alistair Francis
,
2021/12/07
Re: [PATCH v10 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
,
Alistair Francis
,
2021/12/07
Re: [PATCH v3 1/1] target/riscv: Fix PMP propagation for tlb
,
Alistair Francis
,
2021/12/07
Re: [PATCH v3 1/1] target/riscv: Fix PMP propagation for tlb
,
Alistair Francis
,
2021/12/07
Re: [PATCH v3 1/1] target/riscv: Fix PMP propagation for tlb
,
Alistair Francis
,
2021/12/16
Re: [PATCH v3 1/1] target/riscv: Fix PMP propagation for tlb
,
LIU Zhiwei
,
2021/12/16
Re: [PATCH v3 1/1] target/riscv: Fix PMP propagation for tlb
,
LIU Zhiwei
,
2021/12/16
Re: [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Anup Patel
,
2021/12/07
Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target
,
Frédéric Pétrot
,
2021/12/06
Re: [PATCH v2 01/13] hw/sd/ssi-sd: Do not create SD card within controller's realize
,
Markus Armbruster
,
2021/12/06
Re: [PATCH v2 01/13] hw/sd/ssi-sd: Do not create SD card within controller's realize
,
Peter Maydell
,
2021/12/06
Re: [PATCH v1 00/12] Add riscv kvm accel support
,
Michal Prívozník
,
2021/12/03
Re: [PATCH v1 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Anup Patel
,
2021/12/03
RE: [PATCH v1 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Jiangyifei
,
2021/12/10
Re: [PATCH v1 09/12] target/riscv: Add host cpu type
,
Anup Patel
,
2021/12/03
Re: [PATCH v1 07/12] target/riscv: Support setting external interrupt by KVM
,
Anup Patel
,
2021/12/03
RE: [PATCH v1 07/12] target/riscv: Support setting external interrupt by KVM
,
Jiangyifei
,
2021/12/10
Re: [PATCH v1 06/12] target/riscv: Support start kernel directly by KVM
,
Anup Patel
,
2021/12/03
RE: [PATCH v1 06/12] target/riscv: Support start kernel directly by KVM
,
Jiangyifei
,
2021/12/10
Re: [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers
,
Anup Patel
,
2021/12/03
RE: [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers
,
Jiangyifei
,
2021/12/10
Re: [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers
,
Anup Patel
,
2021/12/03
RE: [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers
,
Jiangyifei
,
2021/12/10
Re: [PATCH v1 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Anup Patel
,
2021/12/03
Re: [PATCH v1 01/12] update-linux-headers: Add asm-riscv/kvm.h
,
Anup Patel
,
2021/12/03
Re: [PATCH v6 08/18] target/riscv: moving some insns close to similar insns
,
Alistair Francis
,
2021/12/01
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