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[PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension vi
From: |
Bin Meng |
Subject: |
[PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs |
Date: |
Thu, 21 Apr 2022 08:33:18 +0800 |
This adds initial support for the Sdtrig extension via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented is 2, which is the number that we can
find in the SiFive U54/U74 cores.
[1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
Changes in v5:
- rebase against riscv-to-apply.next
- drop patch 1 in v4 which is already in riscv-to-apply.next
- adjust patch order to let patch 2 in v4 come later
Changes in v4:
- move riscv_trigger_init() call to riscv_cpu_reset()
Changes in v3:
- add riscv_trigger_init(), moved from patch #1 to this patch
- enable debug feature by default for all CPUs
Changes in v2:
- use 0 instead of GETPC()
- change the config option to 'disabled' by default
- new patch: add debug state description
Bin Meng (6):
target/riscv: debug: Implement debug related TCGCPUOps
target/riscv: cpu: Add a config option for native debug
target/riscv: csr: Hook debug CSR read/write
target/riscv: machine: Add debug state description
target/riscv: cpu: Enable native debug feature
hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
include/hw/core/tcg-cpu-ops.h | 1 +
target/riscv/cpu.h | 4 +-
target/riscv/debug.h | 6 ++
target/riscv/cpu.c | 12 ++++
target/riscv/csr.c | 57 +++++++++++++++++++
target/riscv/debug.c | 102 ++++++++++++++++++++++++++++++++++
target/riscv/machine.c | 32 +++++++++++
7 files changed, 213 insertions(+), 1 deletion(-)
--
2.25.1
- [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs,
Bin Meng <=
- [PATCH v5 1/6] target/riscv: debug: Implement debug related TCGCPUOps, Bin Meng, 2022/04/20
- [PATCH v5 2/6] target/riscv: cpu: Add a config option for native debug, Bin Meng, 2022/04/20
- [PATCH v5 3/6] target/riscv: csr: Hook debug CSR read/write, Bin Meng, 2022/04/20
- [PATCH v5 4/6] target/riscv: machine: Add debug state description, Bin Meng, 2022/04/20
- [PATCH v5 5/6] target/riscv: cpu: Enable native debug feature, Bin Meng, 2022/04/20
- [PATCH v5 6/6] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(), Bin Meng, 2022/04/20
- Re: [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs, Alistair Francis, 2022/04/20