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[PATCH v5 6/6] hw/core: tcg-cpu-ops.h: Update comments of debug_check_wa
From: |
Bin Meng |
Subject: |
[PATCH v5 6/6] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() |
Date: |
Thu, 21 Apr 2022 08:33:24 +0800 |
From: Bin Meng <bin.meng@windriver.com>
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index e13898553a..f98671ff32 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -90,6 +90,7 @@ struct TCGCPUOps {
/**
* @debug_check_watchpoint: return true if the architectural
* watchpoint whose address has matched should really fire, used by ARM
+ * and RISC-V
*/
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
--
2.25.1
- [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs, Bin Meng, 2022/04/20
- [PATCH v5 1/6] target/riscv: debug: Implement debug related TCGCPUOps, Bin Meng, 2022/04/20
- [PATCH v5 2/6] target/riscv: cpu: Add a config option for native debug, Bin Meng, 2022/04/20
- [PATCH v5 3/6] target/riscv: csr: Hook debug CSR read/write, Bin Meng, 2022/04/20
- [PATCH v5 4/6] target/riscv: machine: Add debug state description, Bin Meng, 2022/04/20
- [PATCH v5 5/6] target/riscv: cpu: Enable native debug feature, Bin Meng, 2022/04/20
- [PATCH v5 6/6] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(),
Bin Meng <=
- Re: [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs, Alistair Francis, 2022/04/20