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[PATCH v3 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
From: |
Bin Meng |
Subject: |
[PATCH v3 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC |
Date: |
Sun, 11 Dec 2022 11:08:16 +0800 |
Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build")
the IBEX PLIC model was replaced with the SiFive PLIC model in the
'opentitan' machine but we forgot the add the dependency there.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 167dc4cca6..1e4b58024f 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -19,6 +19,7 @@ config MICROCHIP_PFSOC
config OPENTITAN
bool
select IBEX
+ select SIFIVE_PLIC
select UNIMP
config SHAKTI_C
--
2.34.1
- [PATCH v3 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Bin Meng, 2022/12/10
- [PATCH v3 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order, Bin Meng, 2022/12/10
- [PATCH v3 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC,
Bin Meng <=
- [PATCH v3 05/16] hw/riscv: spike: Remove misleading comments, Bin Meng, 2022/12/10
- [PATCH v3 06/16] hw/intc: sifive_plic: Drop PLICMode_H, Bin Meng, 2022/12/10
- [PATCH v3 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Bin Meng, 2022/12/10
- [PATCH v3 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), Bin Meng, 2022/12/10
- [PATCH v3 09/16] hw/intc: sifive_plic: Update "num-sources" property default value, Bin Meng, 2022/12/10
- [PATCH v3 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Bin Meng, 2022/12/10
- [PATCH v3 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Bin Meng, 2022/12/10
- [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/10
- [PATCH v3 11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/10
- [PATCH v3 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Bin Meng, 2022/12/10