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Re: [PATCH v3 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priori
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization |
Date: |
Mon, 12 Dec 2022 15:45:29 +1000 |
On Sun, Dec 11, 2022 at 1:22 PM Bin Meng <bmeng@tinylab.org> wrote:
>
> "hartid-base" and "priority-base" are zero by default. There is no
> need to initialize them to zero again.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> (no changes since v1)
>
> hw/riscv/opentitan.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 78f895d773..85ffdac5be 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -173,10 +173,8 @@ static void lowrisc_ibex_soc_realize(DeviceState
> *dev_soc, Error **errp)
>
> /* PLIC */
> qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
> - qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
> qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
> qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
> - qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
> qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
> qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
> qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
> --
> 2.34.1
>
>
- [PATCH v3 06/16] hw/intc: sifive_plic: Drop PLICMode_H, (continued)
- [PATCH v3 06/16] hw/intc: sifive_plic: Drop PLICMode_H, Bin Meng, 2022/12/10
- [PATCH v3 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Bin Meng, 2022/12/10
- [PATCH v3 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), Bin Meng, 2022/12/10
- [PATCH v3 09/16] hw/intc: sifive_plic: Update "num-sources" property default value, Bin Meng, 2022/12/10
- [PATCH v3 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Bin Meng, 2022/12/10
- [PATCH v3 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Bin Meng, 2022/12/10
- [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/10
- [PATCH v3 11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/10
- [PATCH v3 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Bin Meng, 2022/12/10
- [PATCH v3 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization, Bin Meng, 2022/12/10
- Re: [PATCH v3 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization,
Alistair Francis <=
- [PATCH v3 16/16] hw/intc: sifive_plic: Fix the pending register range check, Bin Meng, 2022/12/10