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[PULL 01/59] target/riscv: introduce riscv_cpu_cfg()
From: |
Palmer Dabbelt |
Subject: |
[PULL 01/59] target/riscv: introduce riscv_cpu_cfg() |
Date: |
Fri, 3 Mar 2023 00:36:42 -0800 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230222185205.355361-2-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/cpu.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 31537fc05f..7ee22cbfa1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -654,6 +654,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
#endif
#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
+static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
+{
+ return &env_archcpu(env)->cfg;
+}
+
#if defined(TARGET_RISCV32)
#define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
#else
--
2.39.2
- [PULL 00/59] Fifth RISC-V PR for QEMU 8.0, Palmer Dabbelt, 2023/03/03
- [PULL 01/59] target/riscv: introduce riscv_cpu_cfg(),
Palmer Dabbelt <=
- [PULL 05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP, Palmer Dabbelt, 2023/03/03
- [PULL 04/59] target/riscv: remove RISCV_FEATURE_DEBUG, Palmer Dabbelt, 2023/03/03
- [PULL 07/59] target/riscv: remove RISCV_FEATURE_PMP, Palmer Dabbelt, 2023/03/03
- [PULL 08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus(), Palmer Dabbelt, 2023/03/03
- [PULL 12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx, Palmer Dabbelt, 2023/03/03
- [PULL 02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa(), Palmer Dabbelt, 2023/03/03
- [PULL 03/59] target/riscv: allow MISA writes as experimental, Palmer Dabbelt, 2023/03/03
- [PULL 06/59] target/riscv: remove RISCV_FEATURE_EPMP, Palmer Dabbelt, 2023/03/03
- [PULL 10/59] target/riscv/cpu: remove CPUArchState::features and friends, Palmer Dabbelt, 2023/03/03
- [PULL 09/59] target/riscv: remove RISCV_FEATURE_MMU, Palmer Dabbelt, 2023/03/03