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[PULL 03/59] target/riscv: allow MISA writes as experimental
From: |
Palmer Dabbelt |
Subject: |
[PULL 03/59] target/riscv: allow MISA writes as experimental |
Date: |
Fri, 3 Mar 2023 00:36:44 -0800 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
At this moment, and apparently since ever, we have no way of enabling
RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
the nuts and bolts that handles how to properly write this CSR, has
always been a no-op as well because write_misa() will always exit
earlier.
This seems to be benign in the majority of cases. Booting an Ubuntu
'virt' guest and logging all the calls to 'write_misa' shows that no
writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling
RISC-V extensions after the machine is powered on, seems to be a niche
use.
After discussions in the mailing list, most notably in [1], we reached
the consensus that this code is not suited to be exposed to users
because it's not well tested, but at the same time removing it is a bit
extreme because we would like to fix it, and it's easier to do so with
the code available to use instead of fetching it from git log.
The approach taken here is to get rid of RISCV_FEATURE_MISA altogether
and use a new experimental flag called x-misa-w. The default value is
false, meaning that we're keeping the existing behavior of doing nothing
if a write_misa() is attempted. As with any existing experimental flag,
x-misa-w is also a temporary flag that we need to remove once we fix
write_misa().
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg05092.html
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-4-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/cpu.c | 6 ++++++
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 2 +-
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 93b52b826c..1d637b1acd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1210,6 +1210,12 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
+
+ /*
+ * write_misa() is marked as experimental for now so mark
+ * it with -x and default to 'false'.
+ */
+ DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7ee22cbfa1..ca828424c1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -89,7 +89,6 @@ enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
- RISCV_FEATURE_MISA,
RISCV_FEATURE_DEBUG
};
@@ -498,6 +497,7 @@ struct RISCVCPUConfig {
bool pmp;
bool epmp;
bool debug;
+ bool misa_w;
bool short_isa_string;
};
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e149b453da..3cb8d2ffad 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1329,7 +1329,7 @@ static RISCVException read_misa(CPURISCVState *env, int
csrno,
static RISCVException write_misa(CPURISCVState *env, int csrno,
target_ulong val)
{
- if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
+ if (!riscv_cpu_cfg(env)->misa_w) {
/* drop write to misa */
return RISCV_EXCP_NONE;
}
--
2.39.2
- [PULL 00/59] Fifth RISC-V PR for QEMU 8.0, Palmer Dabbelt, 2023/03/03
- [PULL 01/59] target/riscv: introduce riscv_cpu_cfg(), Palmer Dabbelt, 2023/03/03
- [PULL 05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP, Palmer Dabbelt, 2023/03/03
- [PULL 04/59] target/riscv: remove RISCV_FEATURE_DEBUG, Palmer Dabbelt, 2023/03/03
- [PULL 07/59] target/riscv: remove RISCV_FEATURE_PMP, Palmer Dabbelt, 2023/03/03
- [PULL 08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus(), Palmer Dabbelt, 2023/03/03
- [PULL 12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx, Palmer Dabbelt, 2023/03/03
- [PULL 02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa(), Palmer Dabbelt, 2023/03/03
- [PULL 03/59] target/riscv: allow MISA writes as experimental,
Palmer Dabbelt <=
- [PULL 06/59] target/riscv: remove RISCV_FEATURE_EPMP, Palmer Dabbelt, 2023/03/03
- [PULL 10/59] target/riscv/cpu: remove CPUArchState::features and friends, Palmer Dabbelt, 2023/03/03
- [PULL 09/59] target/riscv: remove RISCV_FEATURE_MMU, Palmer Dabbelt, 2023/03/03
- [PULL 14/59] target/riscv: Add cfg properties for Zv* extensions, Palmer Dabbelt, 2023/03/03
- [PULL 11/59] target/riscv: Fix the relationship between Zfhmin and Zfh, Palmer Dabbelt, 2023/03/03
- [PULL 15/59] target/riscv: Fix relationship between V, Zve*, F and D, Palmer Dabbelt, 2023/03/03
- [PULL 13/59] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Palmer Dabbelt, 2023/03/03
- [PULL 18/59] target/riscv: Simplify check for Zve32f and Zve64f, Palmer Dabbelt, 2023/03/03
- [PULL 19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc, Palmer Dabbelt, 2023/03/03
- [PULL 16/59] target/riscv: Add property check for Zvfh{min} extensions, Palmer Dabbelt, 2023/03/03