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[PATCH 03/65] target/riscv: Add properties for XTheadVector extension
From: |
Huang Tao |
Subject: |
[PATCH 03/65] target/riscv: Add properties for XTheadVector extension |
Date: |
Fri, 12 Apr 2024 15:36:33 +0800 |
Add ext_xtheadvector properties.
In this patch, we add ext_xtheadvector in RISCVCPUConfig
for XTheadVector as a start. In rv64_thead_c906_cpu_init,
we make ext_xtheadvector equals false to avoid affecting
other extensions when it is not fully implemented.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/cpu.c | 3 +++
target/riscv/cpu_cfg.h | 2 ++
target/riscv/cpu_helper.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 33 +++++++++++++++++++++++++++++++++
4 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3f21c976ba..05652e8c87 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -201,6 +201,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
+ ISA_EXT_DATA_ENTRY(xtheadvector, PRIV_VERSION_1_11_0, ext_xtheadvector),
ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0,
ext_XVentanaCondOps),
DEFINE_PROP_END_OF_LIST(),
@@ -541,6 +542,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
cpu->cfg.ext_xtheadmemidx = true;
cpu->cfg.ext_xtheadmempair = true;
cpu->cfg.ext_xtheadsync = true;
+ cpu->cfg.ext_xtheadvector = false;
cpu->cfg.mvendorid = THEAD_VENDOR_ID;
#ifndef CONFIG_USER_ONLY
@@ -1567,6 +1569,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false),
MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
+ MULTI_EXT_CFG_BOOL("xtheadvector", ext_xtheadvector, false),
MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
DEFINE_PROP_END_OF_LIST(),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index cb750154bd..da85e94e04 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -149,6 +149,7 @@ struct RISCVCPUConfig {
bool ext_xtheadmemidx;
bool ext_xtheadmempair;
bool ext_xtheadsync;
+ bool ext_xtheadvector;
bool ext_XVentanaCondOps;
uint32_t pmu_mask;
@@ -205,6 +206,7 @@ MATERIALISE_EXT_PREDICATE(xtheadmac)
MATERIALISE_EXT_PREDICATE(xtheadmemidx)
MATERIALISE_EXT_PREDICATE(xtheadmempair)
MATERIALISE_EXT_PREDICATE(xtheadsync)
+MATERIALISE_EXT_PREDICATE(xtheadvector)
MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
#endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index fc090d729a..5882b65321 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -72,7 +72,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
- if (cpu->cfg.ext_zve32f) {
+ if (cpu->cfg.ext_zve32f || cpu->cfg.ext_xtheadvector) {
/*
* If env->vl equals to VLMAX, we can use generic vector operation
* expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 483774e4f8..f7a105b30e 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -281,6 +281,25 @@ static void riscv_cpu_validate_v(CPURISCVState *env,
RISCVCPUConfig *cfg,
}
}
+static void th_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
+ Error **errp)
+{
+ uint32_t vlen = cfg->vlenb << 3;
+
+ if (vlen < 32) {
+ error_setg(errp,
+ "In XTheadVector extension, VLEN must be "
+ "greater than or equal to 32");
+ }
+
+ if (vlen < cfg->elen) {
+ error_setg(errp,
+ "In XTheadVector extension, VLEN must be "
+ "greater than or equal to ELEN");
+ return;
+ }
+}
+
static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
{
CPURISCVState *env = &cpu->env;
@@ -485,6 +504,20 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
return;
}
+ if (cpu->cfg.ext_xtheadvector && riscv_has_ext(env, RVV)) {
+ error_setg(errp, "XTheadVector extension is incompatible with "
+ "RVV extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_xtheadvector) {
+ th_cpu_validate_v(env, &cpu->cfg, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ }
+
if (riscv_has_ext(env, RVV)) {
riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
if (local_err != NULL) {
--
2.44.0
- [PATCH 00/65]target/riscv: Support XTheadVector extension, Huang Tao, 2024/04/12
- [PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation, Huang Tao, 2024/04/12
- [PATCH 02/65] target/riscv: Reuse th_csr.c to add user-mode csrs, Huang Tao, 2024/04/12
- [PATCH 03/65] target/riscv: Add properties for XTheadVector extension,
Huang Tao <=
- [PATCH 04/65] target/riscv: Override some csr ops for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 05/65] target/riscv: Add mlen in DisasContext, Huang Tao, 2024/04/12
- [PATCH 06/65] target/riscv: Implement insns decode rules for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 07/65] target/riscv: implement th.vsetvl{i} for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 08/65] target/riscv: Add strided load instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 09/65] target/riscv: Add strided store instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 10/65] target/riscv: Add unit-stride load instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 11/65] target/riscv: Add unit-stride store instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 12/65] target/riscv: Add indexed load instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 13/65] target/riscv: Add indexed store instructions for XTheadVector, Huang Tao, 2024/04/12