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[PATCH 05/65] target/riscv: Add mlen in DisasContext
From: |
Huang Tao |
Subject: |
[PATCH 05/65] target/riscv: Add mlen in DisasContext |
Date: |
Fri, 12 Apr 2024 15:36:35 +0800 |
The mask register layout of XTheadVector is different from that of RVV1.0.
For RVV1.0, the mask bits for element i are located in bit[i] of the mask
register. While for XTheadVector, the mask bits for element i are located
bit[MLEN*i] of the mask register. (MLEN = SEW/LMUL)
So we add mlen in DisasContext to indicate the mask bit and reduce the
calculation of mlen.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/translate.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7eb8c9cd31..a22fdb59df 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -106,6 +106,7 @@ typedef struct DisasContext {
bool cfg_vta_all_1s;
bool vstart_eq_zero;
bool vl_eq_vlmax;
+ uint16_t mlen;
CPUState *cs;
TCGv zero;
/* PointerMasking extension */
@@ -1207,6 +1208,9 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->zero = tcg_constant_tl(0);
ctx->virt_inst_excp = false;
ctx->decoders = cpu->decoders;
+ if (cpu->cfg.ext_xtheadvector) {
+ ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
+ }
}
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
--
2.44.0
- [PATCH 00/65]target/riscv: Support XTheadVector extension, Huang Tao, 2024/04/12
- [PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation, Huang Tao, 2024/04/12
- [PATCH 02/65] target/riscv: Reuse th_csr.c to add user-mode csrs, Huang Tao, 2024/04/12
- [PATCH 03/65] target/riscv: Add properties for XTheadVector extension, Huang Tao, 2024/04/12
- [PATCH 04/65] target/riscv: Override some csr ops for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 05/65] target/riscv: Add mlen in DisasContext,
Huang Tao <=
- [PATCH 06/65] target/riscv: Implement insns decode rules for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 07/65] target/riscv: implement th.vsetvl{i} for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 08/65] target/riscv: Add strided load instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 09/65] target/riscv: Add strided store instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 10/65] target/riscv: Add unit-stride load instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 11/65] target/riscv: Add unit-stride store instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 12/65] target/riscv: Add indexed load instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 13/65] target/riscv: Add indexed store instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 14/65] target/riscv: Add unit-stride fault-only-first instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 15/65] target/riscv: Add vector amo operations for XTheadVector, Huang Tao, 2024/04/12