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[PATCH 22/65] target/riscv: Add integer compare instructions for XTheadV
From: |
Huang Tao |
Subject: |
[PATCH 22/65] target/riscv: Add integer compare instructions for XTheadVector |
Date: |
Fri, 12 Apr 2024 15:36:52 +0800 |
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 57 ++++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 69 +++++++---
target/riscv/xtheadvector_helper.c | 127 ++++++++++++++++++
3 files changed, 233 insertions(+), 20 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d3170ba91f..8f2dec158b 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1638,3 +1638,60 @@ DEF_HELPER_6(th_vnsrl_vx_w, void, ptr, ptr, tl, ptr,
env, i32)
DEF_HELPER_6(th_vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(th_vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmseq_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmseq_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsne_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsne_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsne_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsne_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsltu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsltu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsltu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsltu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmslt_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmslt_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmslt_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmslt_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsleu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsleu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsleu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsleu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsle_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsle_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsle_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmsle_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmseq_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmseq_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmseq_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmseq_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsne_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsne_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsne_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsne_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsltu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsltu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsltu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsltu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmslt_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmslt_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmslt_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmslt_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsleu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsleu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsleu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsleu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsle_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsle_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsle_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsle_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsgtu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsgtu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsgtu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsgtu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsgt_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsgt_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsgt_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vmsgt_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 68810ff0ec..049d9da0a5 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -1470,32 +1470,61 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
GEN_OPIVI_NARROW_TRANS_TH(th_vnsra_vi, IMM_ZX, th_vnsra_vx)
GEN_OPIVI_NARROW_TRANS_TH(th_vnsrl_vi, IMM_ZX, th_vnsrl_vx)
+/* Vector Integer Comparison Instructions */
+
+/*
+ * For all comparison instructions, an illegal instruction exception is raised
+ * if the destination vector register overlaps a source vector register group
+ * and LMUL > 1.
+ */
+static bool opivv_cmp_check_th(DisasContext *s, arg_rmrr *a)
+{
+ return (require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ th_check_reg(s, a->rs2, false) &&
+ th_check_reg(s, a->rs1, false) &&
+ ((th_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
+ th_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
+ (s->lmul == 0)));
+}
+GEN_OPIVV_TRANS_TH(th_vmseq_vv, opivv_cmp_check_th)
+GEN_OPIVV_TRANS_TH(th_vmsne_vv, opivv_cmp_check_th)
+GEN_OPIVV_TRANS_TH(th_vmsltu_vv, opivv_cmp_check_th)
+GEN_OPIVV_TRANS_TH(th_vmslt_vv, opivv_cmp_check_th)
+GEN_OPIVV_TRANS_TH(th_vmsleu_vv, opivv_cmp_check_th)
+GEN_OPIVV_TRANS_TH(th_vmsle_vv, opivv_cmp_check_th)
+
+static bool opivx_cmp_check_th(DisasContext *s, arg_rmrr *a)
+{
+ return (require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ th_check_reg(s, a->rs2, false) &&
+ (th_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
+ (s->lmul == 0)));
+}
+
+GEN_OPIVX_TRANS_TH(th_vmseq_vx, opivx_cmp_check_th)
+GEN_OPIVX_TRANS_TH(th_vmsne_vx, opivx_cmp_check_th)
+GEN_OPIVX_TRANS_TH(th_vmsltu_vx, opivx_cmp_check_th)
+GEN_OPIVX_TRANS_TH(th_vmslt_vx, opivx_cmp_check_th)
+GEN_OPIVX_TRANS_TH(th_vmsleu_vx, opivx_cmp_check_th)
+GEN_OPIVX_TRANS_TH(th_vmsle_vx, opivx_cmp_check_th)
+GEN_OPIVX_TRANS_TH(th_vmsgtu_vx, opivx_cmp_check_th)
+GEN_OPIVX_TRANS_TH(th_vmsgt_vx, opivx_cmp_check_th)
+
+GEN_OPIVI_TRANS_TH(th_vmseq_vi, IMM_SX, th_vmseq_vx, opivx_cmp_check_th)
+GEN_OPIVI_TRANS_TH(th_vmsne_vi, IMM_SX, th_vmsne_vx, opivx_cmp_check_th)
+GEN_OPIVI_TRANS_TH(th_vmsleu_vi, IMM_ZX, th_vmsleu_vx, opivx_cmp_check_th)
+GEN_OPIVI_TRANS_TH(th_vmsle_vi, IMM_SX, th_vmsle_vx, opivx_cmp_check_th)
+GEN_OPIVI_TRANS_TH(th_vmsgtu_vi, IMM_ZX, th_vmsgtu_vx, opivx_cmp_check_th)
+GEN_OPIVI_TRANS_TH(th_vmsgt_vi, IMM_SX, th_vmsgt_vx, opivx_cmp_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vmseq_vv)
-TH_TRANS_STUB(th_vmseq_vx)
-TH_TRANS_STUB(th_vmseq_vi)
-TH_TRANS_STUB(th_vmsne_vv)
-TH_TRANS_STUB(th_vmsne_vx)
-TH_TRANS_STUB(th_vmsne_vi)
-TH_TRANS_STUB(th_vmsltu_vv)
-TH_TRANS_STUB(th_vmsltu_vx)
-TH_TRANS_STUB(th_vmslt_vv)
-TH_TRANS_STUB(th_vmslt_vx)
-TH_TRANS_STUB(th_vmsleu_vv)
-TH_TRANS_STUB(th_vmsleu_vx)
-TH_TRANS_STUB(th_vmsleu_vi)
-TH_TRANS_STUB(th_vmsle_vv)
-TH_TRANS_STUB(th_vmsle_vx)
-TH_TRANS_STUB(th_vmsle_vi)
-TH_TRANS_STUB(th_vmsgtu_vx)
-TH_TRANS_STUB(th_vmsgtu_vi)
-TH_TRANS_STUB(th_vmsgt_vx)
-TH_TRANS_STUB(th_vmsgt_vi)
TH_TRANS_STUB(th_vminu_vv)
TH_TRANS_STUB(th_vminu_vx)
TH_TRANS_STUB(th_vmin_vv)
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index f4bd80349d..827650b325 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -1415,3 +1415,130 @@ GEN_TH_SHIFT_VX(th_vnsra_vx_h, int16_t, int32_t, H2,
H4, TH_SRL,
0x1f, clearh_th)
GEN_TH_SHIFT_VX(th_vnsra_vx_w, int32_t, int64_t, H4, H8, TH_SRL,
0x3f, clearl_th)
+
+/* Vector Integer Comparison Instructions */
+#define TH_MSEQ(N, M) (N == M)
+#define TH_MSNE(N, M) (N != M)
+#define TH_MSLT(N, M) (N < M)
+#define TH_MSLE(N, M) (N <= M)
+#define TH_MSGT(N, M) (N > M)
+
+#define GEN_TH_CMP_VV(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t mlen = th_mlen(desc); \
+ uint32_t vm = th_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = th_maxsz(desc) / sizeof(ETYPE); \
+ uint32_t i; \
+ \
+ VSTART_CHECK_EARLY_EXIT(env); \
+ for (i = env->vstart; i < vl; i++) { \
+ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ if (!vm && !th_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ th_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \
+ } \
+ env->vstart = 0; \
+ for (; i < vlmax; i++) { \
+ th_set_elem_mask(vd, mlen, i, 0); \
+ } \
+}
+
+GEN_TH_CMP_VV(th_vmseq_vv_b, uint8_t, H1, TH_MSEQ)
+GEN_TH_CMP_VV(th_vmseq_vv_h, uint16_t, H2, TH_MSEQ)
+GEN_TH_CMP_VV(th_vmseq_vv_w, uint32_t, H4, TH_MSEQ)
+GEN_TH_CMP_VV(th_vmseq_vv_d, uint64_t, H8, TH_MSEQ)
+
+GEN_TH_CMP_VV(th_vmsne_vv_b, uint8_t, H1, TH_MSNE)
+GEN_TH_CMP_VV(th_vmsne_vv_h, uint16_t, H2, TH_MSNE)
+GEN_TH_CMP_VV(th_vmsne_vv_w, uint32_t, H4, TH_MSNE)
+GEN_TH_CMP_VV(th_vmsne_vv_d, uint64_t, H8, TH_MSNE)
+
+GEN_TH_CMP_VV(th_vmsltu_vv_b, uint8_t, H1, TH_MSLT)
+GEN_TH_CMP_VV(th_vmsltu_vv_h, uint16_t, H2, TH_MSLT)
+GEN_TH_CMP_VV(th_vmsltu_vv_w, uint32_t, H4, TH_MSLT)
+GEN_TH_CMP_VV(th_vmsltu_vv_d, uint64_t, H8, TH_MSLT)
+
+GEN_TH_CMP_VV(th_vmslt_vv_b, int8_t, H1, TH_MSLT)
+GEN_TH_CMP_VV(th_vmslt_vv_h, int16_t, H2, TH_MSLT)
+GEN_TH_CMP_VV(th_vmslt_vv_w, int32_t, H4, TH_MSLT)
+GEN_TH_CMP_VV(th_vmslt_vv_d, int64_t, H8, TH_MSLT)
+
+GEN_TH_CMP_VV(th_vmsleu_vv_b, uint8_t, H1, TH_MSLE)
+GEN_TH_CMP_VV(th_vmsleu_vv_h, uint16_t, H2, TH_MSLE)
+GEN_TH_CMP_VV(th_vmsleu_vv_w, uint32_t, H4, TH_MSLE)
+GEN_TH_CMP_VV(th_vmsleu_vv_d, uint64_t, H8, TH_MSLE)
+
+GEN_TH_CMP_VV(th_vmsle_vv_b, int8_t, H1, TH_MSLE)
+GEN_TH_CMP_VV(th_vmsle_vv_h, int16_t, H2, TH_MSLE)
+GEN_TH_CMP_VV(th_vmsle_vv_w, int32_t, H4, TH_MSLE)
+GEN_TH_CMP_VV(th_vmsle_vv_d, int64_t, H8, TH_MSLE)
+
+#define GEN_TH_CMP_VX(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t mlen = th_mlen(desc); \
+ uint32_t vm = th_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = th_maxsz(desc) / sizeof(ETYPE); \
+ uint32_t i; \
+ \
+ VSTART_CHECK_EARLY_EXIT(env); \
+ for (i = env->vstart; i < vl; i++) { \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ if (!vm && !th_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ th_set_elem_mask(vd, mlen, i, \
+ DO_OP(s2, (ETYPE)(target_long)s1)); \
+ } \
+ env->vstart = 0; \
+ for (; i < vlmax; i++) { \
+ th_set_elem_mask(vd, mlen, i, 0); \
+ } \
+}
+
+GEN_TH_CMP_VX(th_vmseq_vx_b, uint8_t, H1, TH_MSEQ)
+GEN_TH_CMP_VX(th_vmseq_vx_h, uint16_t, H2, TH_MSEQ)
+GEN_TH_CMP_VX(th_vmseq_vx_w, uint32_t, H4, TH_MSEQ)
+GEN_TH_CMP_VX(th_vmseq_vx_d, uint64_t, H8, TH_MSEQ)
+
+GEN_TH_CMP_VX(th_vmsne_vx_b, uint8_t, H1, TH_MSNE)
+GEN_TH_CMP_VX(th_vmsne_vx_h, uint16_t, H2, TH_MSNE)
+GEN_TH_CMP_VX(th_vmsne_vx_w, uint32_t, H4, TH_MSNE)
+GEN_TH_CMP_VX(th_vmsne_vx_d, uint64_t, H8, TH_MSNE)
+
+GEN_TH_CMP_VX(th_vmsltu_vx_b, uint8_t, H1, TH_MSLT)
+GEN_TH_CMP_VX(th_vmsltu_vx_h, uint16_t, H2, TH_MSLT)
+GEN_TH_CMP_VX(th_vmsltu_vx_w, uint32_t, H4, TH_MSLT)
+GEN_TH_CMP_VX(th_vmsltu_vx_d, uint64_t, H8, TH_MSLT)
+
+GEN_TH_CMP_VX(th_vmslt_vx_b, int8_t, H1, TH_MSLT)
+GEN_TH_CMP_VX(th_vmslt_vx_h, int16_t, H2, TH_MSLT)
+GEN_TH_CMP_VX(th_vmslt_vx_w, int32_t, H4, TH_MSLT)
+GEN_TH_CMP_VX(th_vmslt_vx_d, int64_t, H8, TH_MSLT)
+
+GEN_TH_CMP_VX(th_vmsleu_vx_b, uint8_t, H1, TH_MSLE)
+GEN_TH_CMP_VX(th_vmsleu_vx_h, uint16_t, H2, TH_MSLE)
+GEN_TH_CMP_VX(th_vmsleu_vx_w, uint32_t, H4, TH_MSLE)
+GEN_TH_CMP_VX(th_vmsleu_vx_d, uint64_t, H8, TH_MSLE)
+
+GEN_TH_CMP_VX(th_vmsle_vx_b, int8_t, H1, TH_MSLE)
+GEN_TH_CMP_VX(th_vmsle_vx_h, int16_t, H2, TH_MSLE)
+GEN_TH_CMP_VX(th_vmsle_vx_w, int32_t, H4, TH_MSLE)
+GEN_TH_CMP_VX(th_vmsle_vx_d, int64_t, H8, TH_MSLE)
+
+GEN_TH_CMP_VX(th_vmsgtu_vx_b, uint8_t, H1, TH_MSGT)
+GEN_TH_CMP_VX(th_vmsgtu_vx_h, uint16_t, H2, TH_MSGT)
+GEN_TH_CMP_VX(th_vmsgtu_vx_w, uint32_t, H4, TH_MSGT)
+GEN_TH_CMP_VX(th_vmsgtu_vx_d, uint64_t, H8, TH_MSGT)
+
+GEN_TH_CMP_VX(th_vmsgt_vx_b, int8_t, H1, TH_MSGT)
+GEN_TH_CMP_VX(th_vmsgt_vx_h, int16_t, H2, TH_MSGT)
+GEN_TH_CMP_VX(th_vmsgt_vx_w, int32_t, H4, TH_MSGT)
+GEN_TH_CMP_VX(th_vmsgt_vx_d, int64_t, H8, TH_MSGT)
--
2.44.0
- [PATCH 12/65] target/riscv: Add indexed load instructions for XTheadVector, (continued)
- [PATCH 12/65] target/riscv: Add indexed load instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 13/65] target/riscv: Add indexed store instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 14/65] target/riscv: Add unit-stride fault-only-first instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 15/65] target/riscv: Add vector amo operations for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 16/65] target/riscv: Add single-width integer add and subtract instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 17/65] target/riscv: Add widening integer add/subtract instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 18/65] target/riscv: Add integer add-with-carry/sub-with-borrow instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 19/65] target/riscv: Add bitwise logical instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 20/65] target/riscv: Add single-width bit shift instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 21/65] target/riscv: Add narrowing integer right shift instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 22/65] target/riscv: Add integer compare instructions for XTheadVector,
Huang Tao <=
- [PATCH 23/65] target/riscv: Add integer min/max instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 24/65] target/riscv: Add single-width integer multiply instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 25/65] target/riscv: Add integer divide instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 26/65] target/riscv: Add widening integer multiply instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 27/65] target/riscv: Add single-width integer multiply-add instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 28/65] target/riscv: Add widening integer multiply-add instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 29/65] target/riscv: Add integer merge and move instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 30/65] target/riscv: Add single-width saturating add and sub instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 31/65] target/riscv: Add single-width average add and sub instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 32/65] target/riscv: Add single-width fractional mul with rounding and saturation for XTheadVector, Huang Tao, 2024/04/12