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[PATCH 26/65] target/riscv: Add widening integer multiply instructions f
From: |
Huang Tao |
Subject: |
[PATCH 26/65] target/riscv: Add widening integer multiply instructions for XTheadVector |
Date: |
Fri, 12 Apr 2024 15:36:56 +0800 |
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 19 +++++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 14 ++++---
target/riscv/vector_helper.c | 3 --
target/riscv/vector_internals.h | 3 ++
target/riscv/xtheadvector_helper.c | 39 +++++++++++++++++++
5 files changed, 69 insertions(+), 9 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 3d5ad2847e..93e6a3f33d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1794,3 +1794,22 @@ DEF_HELPER_6(th_vrem_vx_b, void, ptr, ptr, tl, ptr, env,
i32)
DEF_HELPER_6(th_vrem_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vrem_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vrem_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(th_vwmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmulu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmulu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmulu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmulsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmulsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmulsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmul_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmulu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmulu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmulu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmulsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmulsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmulsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index a609b7faf3..681e967078 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -1549,18 +1549,20 @@ GEN_OPIVX_TRANS_TH(th_vdiv_vx, opivx_check_th)
GEN_OPIVX_TRANS_TH(th_vremu_vx, opivx_check_th)
GEN_OPIVX_TRANS_TH(th_vrem_vx, opivx_check_th)
+/* Vector Widening Integer Multiply Instructions */
+GEN_OPIVV_WIDEN_TRANS_TH(th_vwmul_vv, opivv_widen_check_th)
+GEN_OPIVV_WIDEN_TRANS_TH(th_vwmulu_vv, opivv_widen_check_th)
+GEN_OPIVV_WIDEN_TRANS_TH(th_vwmulsu_vv, opivv_widen_check_th)
+GEN_OPIVX_WIDEN_TRANS_TH(th_vwmul_vx, opivx_widen_check_th)
+GEN_OPIVX_WIDEN_TRANS_TH(th_vwmulu_vx, opivx_widen_check_th)
+GEN_OPIVX_WIDEN_TRANS_TH(th_vwmulsu_vx, opivx_widen_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vwmulu_vv)
-TH_TRANS_STUB(th_vwmulu_vx)
-TH_TRANS_STUB(th_vwmulsu_vv)
-TH_TRANS_STUB(th_vwmulsu_vx)
-TH_TRANS_STUB(th_vwmul_vv)
-TH_TRANS_STUB(th_vwmul_vx)
TH_TRANS_STUB(th_vmacc_vv)
TH_TRANS_STUB(th_vmacc_vx)
TH_TRANS_STUB(th_vnmsac_vv)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 5aba3f238f..b312d67f87 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -647,9 +647,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
*/
/* (TD, T1, T2, TX1, TX2) */
-#define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t
-#define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t
-#define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t
#define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
#define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
#define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index 4cbd7f972a..c3d9752e2e 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -249,6 +249,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
#define WOP_WSSS_B int16_t, int8_t, int16_t, int16_t, int16_t
#define WOP_WSSS_H int32_t, int16_t, int32_t, int32_t, int32_t
#define WOP_WSSS_W int64_t, int32_t, int64_t, int64_t, int64_t
+#define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t
+#define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t
+#define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t
/* share functions */
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index 4af66b047a..b5b1e55452 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -1752,3 +1752,42 @@ GEN_TH_VX(th_vrem_vx_b, 1, 1, clearb_th)
GEN_TH_VX(th_vrem_vx_h, 2, 2, clearh_th)
GEN_TH_VX(th_vrem_vx_w, 4, 4, clearl_th)
GEN_TH_VX(th_vrem_vx_d, 8, 8, clearq_th)
+
+/* Vector Widening Integer Multiply Instructions */
+THCALL(TH_OPIVV2, th_vwmul_vv_b, WOP_SSS_B, H2, H1, H1, TH_MUL)
+THCALL(TH_OPIVV2, th_vwmul_vv_h, WOP_SSS_H, H4, H2, H2, TH_MUL)
+THCALL(TH_OPIVV2, th_vwmul_vv_w, WOP_SSS_W, H8, H4, H4, TH_MUL)
+THCALL(TH_OPIVV2, th_vwmulu_vv_b, WOP_UUU_B, H2, H1, H1, TH_MUL)
+THCALL(TH_OPIVV2, th_vwmulu_vv_h, WOP_UUU_H, H4, H2, H2, TH_MUL)
+THCALL(TH_OPIVV2, th_vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, TH_MUL)
+THCALL(TH_OPIVV2, th_vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, TH_MUL)
+THCALL(TH_OPIVV2, th_vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, TH_MUL)
+THCALL(TH_OPIVV2, th_vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, TH_MUL)
+GEN_TH_VV(th_vwmul_vv_b, 1, 2, clearh_th)
+GEN_TH_VV(th_vwmul_vv_h, 2, 4, clearl_th)
+GEN_TH_VV(th_vwmul_vv_w, 4, 8, clearq_th)
+GEN_TH_VV(th_vwmulu_vv_b, 1, 2, clearh_th)
+GEN_TH_VV(th_vwmulu_vv_h, 2, 4, clearl_th)
+GEN_TH_VV(th_vwmulu_vv_w, 4, 8, clearq_th)
+GEN_TH_VV(th_vwmulsu_vv_b, 1, 2, clearh_th)
+GEN_TH_VV(th_vwmulsu_vv_h, 2, 4, clearl_th)
+GEN_TH_VV(th_vwmulsu_vv_w, 4, 8, clearq_th)
+
+THCALL(TH_OPIVX2, th_vwmul_vx_b, WOP_SSS_B, H2, H1, TH_MUL)
+THCALL(TH_OPIVX2, th_vwmul_vx_h, WOP_SSS_H, H4, H2, TH_MUL)
+THCALL(TH_OPIVX2, th_vwmul_vx_w, WOP_SSS_W, H8, H4, TH_MUL)
+THCALL(TH_OPIVX2, th_vwmulu_vx_b, WOP_UUU_B, H2, H1, TH_MUL)
+THCALL(TH_OPIVX2, th_vwmulu_vx_h, WOP_UUU_H, H4, H2, TH_MUL)
+THCALL(TH_OPIVX2, th_vwmulu_vx_w, WOP_UUU_W, H8, H4, TH_MUL)
+THCALL(TH_OPIVX2, th_vwmulsu_vx_b, WOP_SUS_B, H2, H1, TH_MUL)
+THCALL(TH_OPIVX2, th_vwmulsu_vx_h, WOP_SUS_H, H4, H2, TH_MUL)
+THCALL(TH_OPIVX2, th_vwmulsu_vx_w, WOP_SUS_W, H8, H4, TH_MUL)
+GEN_TH_VX(th_vwmul_vx_b, 1, 2, clearh_th)
+GEN_TH_VX(th_vwmul_vx_h, 2, 4, clearl_th)
+GEN_TH_VX(th_vwmul_vx_w, 4, 8, clearq_th)
+GEN_TH_VX(th_vwmulu_vx_b, 1, 2, clearh_th)
+GEN_TH_VX(th_vwmulu_vx_h, 2, 4, clearl_th)
+GEN_TH_VX(th_vwmulu_vx_w, 4, 8, clearq_th)
+GEN_TH_VX(th_vwmulsu_vx_b, 1, 2, clearh_th)
+GEN_TH_VX(th_vwmulsu_vx_h, 2, 4, clearl_th)
+GEN_TH_VX(th_vwmulsu_vx_w, 4, 8, clearq_th)
--
2.44.0
- [PATCH 16/65] target/riscv: Add single-width integer add and subtract instructions for XTheadVector, (continued)
- [PATCH 16/65] target/riscv: Add single-width integer add and subtract instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 17/65] target/riscv: Add widening integer add/subtract instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 18/65] target/riscv: Add integer add-with-carry/sub-with-borrow instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 19/65] target/riscv: Add bitwise logical instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 20/65] target/riscv: Add single-width bit shift instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 21/65] target/riscv: Add narrowing integer right shift instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 22/65] target/riscv: Add integer compare instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 23/65] target/riscv: Add integer min/max instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 24/65] target/riscv: Add single-width integer multiply instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 25/65] target/riscv: Add integer divide instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 26/65] target/riscv: Add widening integer multiply instructions for XTheadVector,
Huang Tao <=
- [PATCH 27/65] target/riscv: Add single-width integer multiply-add instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 28/65] target/riscv: Add widening integer multiply-add instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 29/65] target/riscv: Add integer merge and move instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 30/65] target/riscv: Add single-width saturating add and sub instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 31/65] target/riscv: Add single-width average add and sub instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 32/65] target/riscv: Add single-width fractional mul with rounding and saturation for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 33/65] target/riscv: Add widening saturating scaled multiply-add instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 34/65] target/riscv: Add single-width scaling shift instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 35/65] target/riscv: Add narrowing fixed-point clip instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 36/65] target/riscv: Add single-width floating-point add/sub instructions for XTheadVector, Huang Tao, 2024/04/12