[PATCH 0/6] target/riscv: Support Zabha extension

[LIU Zhiwei]

Zabha adds support AMO operations for byte and half word. If zacas has been 
implemented,
zabha also adds support amocas.b and amocas.h.

More details is on the specification here:
https://github.com/riscv/riscv-zabha

The implemenation of zabha follows the way of AMOs and zacas.

This patch set is based on these two patch set:
1. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00207.html
2. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00212.html


LIU Zhiwei (6):
  target/riscv: Move gen_amo before implement Zabha
  target/riscv: Add AMO instructions for Zabha
  target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
  target/riscv: Add amocas.[b|h] for Zabha
  target/riscv: Enable zabha for max cpu
  disas/riscv: Support zabha disassemble

 disas/riscv.c                               |  60 ++++++++
 target/riscv/cpu.c                          |   2 +
 target/riscv/cpu_cfg.h                      |   1 +
 target/riscv/insn32.decode                  |  22 +++
 target/riscv/insn_trans/trans_rva.c.inc     |  21 ---
 target/riscv/insn_trans/trans_rvzabha.c.inc | 145 ++++++++++++++++++++
 target/riscv/insn_trans/trans_rvzacas.c.inc |  13 --
 target/riscv/translate.c                    |  36 +++++
 8 files changed, 266 insertions(+), 34 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc

-- 
2.25.1