Re: [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations

[Max Chou]

Hi Richart,

Thank you for your feedback.
This version is created by referencing the gen_sve_ldr translation 
function with the similar assumptions that no mask(predication)/no tail 
agnostic/continuous load & store.
You are right, the expansion is large in this version (over 20 TCG 
instructions that suggested in tcg-op doc).
I will provide next version with the helper function implementation like 
sve_ldN_r in ARM target.

Thank you,
Max

On 2024/6/3 1:45 AM, Richard Henderson wrote:
> On 5/31/24 12:44, Max Chou wrote:
> > The vector unit-stride load/store instructions (e.g. vle8.v/vse8.v)
> > perform continuous load/store. We can replace the corresponding helper
> > functions by TCG ops to copy more data at a time with following
> > assumptions:
> >
> > * Perform virtual address resolution once for entire vector at beginning
> > * Without mask
> > * Without tail agnostic
> > * Both host and target are little endian
> >
> > Signed-off-by: Max Chou <max.chou@sifive.com>
>
> Why are you generating all of this inline?  This expansion is very 
> large.  I would expect you to get better performance with a helper 
> function.
>
> AGAIN, please see the Arm implementation.
>
>
> r~