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qemu-riscv (date)
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Last Modified: Sun Jun 30 2024 23:41:59 -0400
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June 30, 2024
[PATCH 6/6] target/riscv: Enable RV32 CPU support in RV64 QEMU
,
LIU Zhiwei
,
23:41
[PATCH 5/6] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
,
LIU Zhiwei
,
23:41
[PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
LIU Zhiwei
,
23:40
[PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
LIU Zhiwei
,
23:40
[PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
LIU Zhiwei
,
23:39
[PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
,
LIU Zhiwei
,
23:39
[PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU
,
LIU Zhiwei
,
23:39
June 29, 2024
[PATCH v2 11/11] disas/riscv: Support zabha disassemble
,
LIU Zhiwei
,
23:13
[PATCH v2 10/11] target/riscv: Enable zabha for max cpu
,
LIU Zhiwei
,
23:13
[PATCH v2 09/11] target/riscv: Add amocas.[b|h] for Zabha
,
LIU Zhiwei
,
23:12
[PATCH v2 08/11] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
,
LIU Zhiwei
,
23:12
[PATCH v2 07/11] target/riscv: Add AMO instructions for Zabha
,
LIU Zhiwei
,
23:11
[PATCH v2 06/11] target/riscv: Move gen_amo before implement Zabha
,
LIU Zhiwei
,
23:11
[PATCH v2 05/11] target/riscv: Support Zama16b extension
,
LIU Zhiwei
,
23:10
[PATCH v2 04/11] disas/riscv: Support zcmop disassemble
,
LIU Zhiwei
,
23:10
[PATCH v2 03/11] target/riscv: Add zcmop extension
,
LIU Zhiwei
,
23:09
[PATCH v2 02/11] disas/riscv: Support zimop disassemble
,
LIU Zhiwei
,
23:09
[PATCH v2 01/11] target/riscv: Add zimop extension
,
LIU Zhiwei
,
23:08
[PATCH v2 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha
,
LIU Zhiwei
,
23:08
June 28, 2024
Re: [PATCH 1/3] target/riscv: zimop and zcmop extension for riscv
,
Deepak Gupta
,
14:03
[PATCH 3/3] target/riscv: Introduce `compressed zimop` aka `zcmop`
,
Deepak Gupta
,
14:02
[PATCH 2/3] target/riscv: zimop instruction encoding and its implementation
,
Deepak Gupta
,
14:02
[PATCH 1/3] target/riscv: zimop and zcmop extension for riscv
,
Deepak Gupta
,
14:02
[PATCH 1/3] target/riscv: zimop and zcmop extension for riscv
,
Deepak Gupta
,
13:51
[PATCH] target/riscv: Fix the check with vector register multiples of LMUL
,
Zhiwei Jiang
,
09:27
[PATCH] target/riscv: Fix the check with vector register multiples of LMUL
,
Zhiwei Jiang
,
09:27
June 27, 2024
[PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
,
Richard Henderson
,
14:04
[PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
Richard Henderson
,
14:03
[PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame
,
Richard Henderson
,
14:03
[PATCH 0/3] util: Add cpuinfo support for riscv
,
Richard Henderson
,
14:03
Re: [PATCH] tcg/riscv: Fix building on OpenBSD/riscv64
,
Richard Henderson
,
13:20
Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Igor Mammedov
,
08:18
Re: [PATCH v6 0/3] RISC-V: Modularize common match conditions for trigger
,
Alistair Francis
,
05:53
Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8
,
Frank Chang
,
03:42
Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8
,
Frank Chang
,
03:18
[PATCH] tcg/riscv: Fix building on OpenBSD/riscv64
,
Brad Smith
,
00:27
June 26, 2024
[PATCH v6 3/3] target/riscv: Apply modularized matching conditions for icount trigger
,
Alvin Chang
,
23:16
[PATCH v6 2/3] target/riscv: Apply modularized matching conditions for watchpoint
,
Alvin Chang
,
23:16
[PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger
,
Alvin Chang
,
23:15
[PATCH v6 0/3] RISC-V: Modularize common match conditions for trigger
,
Alvin Chang
,
23:15
RE: [PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger
,
張哲嘉
,
22:37
[PATCH v6 3/3] target/riscv: Apply modularized matching conditions for icount trigger
,
alvinga
,
22:35
[PATCH v6 2/3] target/riscv: Apply modularized matching conditions for watchpoint
,
alvinga
,
22:35
[PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger
,
alvinga
,
22:34
[PATCH v6 0/3] RISC-V: Modularize common match conditions for trigger
,
alvinga
,
22:34
Re: [PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger
,
Alistair Francis
,
22:18
[PATCH v7 11/11] target/riscv: Do not setup pmu timer if OF is disabled
,
Atish Patra
,
19:57
[PATCH v7 09/11] target/riscv: Start counters from both mhpmcounter and mcountinhibit
,
Atish Patra
,
19:57
[PATCH v7 10/11] target/riscv: More accurately model priv mode filtering.
,
Atish Patra
,
19:57
[PATCH v7 08/11] target/riscv: Enforce WARL behavior for scounteren/hcounteren
,
Atish Patra
,
19:57
[PATCH v7 07/11] target/riscv: Save counter values during countinhibit update
,
Atish Patra
,
19:57
[PATCH v7 06/11] target/riscv: Implement privilege mode filtering for cycle/instret
,
Atish Patra
,
19:57
[PATCH v7 05/11] target/riscv: Add cycle & instret privilege mode filtering support
,
Atish Patra
,
19:57
[PATCH v7 04/11] target/riscv: Add cycle & instret privilege mode filtering definitions
,
Atish Patra
,
19:57
[PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties
,
Atish Patra
,
19:57
[PATCH v7 02/11] target/riscv: Fix the predicate functions for mhpmeventhX CSRs
,
Atish Patra
,
19:57
[PATCH v7 01/11] target/riscv: Combine set_mode and set_virt functions.
,
Atish Patra
,
19:57
[PATCH v7 00/11] Add RISC-V ISA extension smcntrpmf support
,
Atish Patra
,
19:57
Re: [PATCH v8] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI
,
Andrew Jones
,
11:18
[PATCH] tcg/riscv: Fix building on OpenBSD/riscv64
,
Brad Smith
,
09:35
[PATCH v6 3/3] target/riscv: Apply modularized matching conditions for icount trigger
,
Alvin Chang
,
09:24
[PATCH v6 2/3] target/riscv: Apply modularized matching conditions for watchpoint
,
Alvin Chang
,
09:23
[PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger
,
Alvin Chang
,
09:23
[PATCH v6 0/3] RISC-V: Modularize common match conditions for trigger
,
Alvin Chang
,
09:23
Re: [PATCH] tcg/riscv: Fix building on OpenBSD/riscv64
,
Daniel Henrique Barboza
,
06:11
[PATCH] disas/riscv: Add decode for Zawrs extension
,
Rob Bradford
,
05:42
Re: [PATCH v5 1/4] target/riscv: Add functions for common matching conditions of trigger
,
Alistair Francis
,
05:32
Re: [PATCH v4 01/14] exec/memtxattr: add process identifier to the transaction attributes
,
Jason Chien
,
04:10
Re: [RFC PATCH v3 2/2] tests/qtest: QTest example for RISC-V CSR register
,
Thomas Huth
,
03:58
Re: [RFC PATCH v3 1/2] target/riscv: Add RISC-V CSR qtest support
,
Thomas Huth
,
03:56
RE: [PATCH v5 1/4] target/riscv: Add functions for common matching conditions of trigger
,
張哲嘉
,
03:27
Re: [PATCH v5 1/4] target/riscv: Add functions for common matching conditions of trigger
,
Alistair Francis
,
02:20
Re: [PATCH v2 0/6] target/riscv: Add support for Control Transfer Records Ext.
,
Jason Chien
,
02:18
Re: [PATCH v2 2/6] target/riscv: Add Control Transfer Records CSR definitions.
,
Jason Chien
,
02:00
Re: [PATCH v7 2/2] hw/riscv/virt: Add IOPMP support
,
Ethan Chen
,
01:53
June 25, 2024
Re: [PATCH v2 4/6] target/riscv: Add support to record CTR entries.
,
Jason Chien
,
23:49
Re: [PATCH v4 14/14] docs/specs: add riscv-iommu
,
Alistair Francis
,
23:24
Re: [PATCH v4 06/14] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
,
Alistair Francis
,
23:12
Re: [PATCH v3 0/6] Introduce extension implied rules
,
Alistair Francis
,
21:44
Re: [PATCH v7 2/2] hw/riscv/virt: Add IOPMP support
,
Alistair Francis
,
21:25
Re: [PATCH v4 07/14] test/qtest: add riscv-iommu-pci tests
,
Alistair Francis
,
21:13
Re: [PATCH v2 2/6] target/riscv: Add Control Transfer Records CSR definitions.
,
Alistair Francis
,
21:11
Re: [PATCH v4 02/14] hw/riscv: add riscv-iommu-bits.h
,
Alistair Francis
,
21:10
Re: [PATCH v4 01/14] exec/memtxattr: add process identifier to the transaction attributes
,
Alistair Francis
,
21:06
Re: [PATCH v2 0/6] target/riscv: Add support for Control Transfer Records Ext.
,
Alistair Francis
,
20:12
Re: [PATCH v3 1/6] target/riscv: Introduce extension implied rules definition
,
Alistair Francis
,
20:04
Re: [PATCH v3 2/6] target/riscv: Introduce extension implied rule helpers
,
Alistair Francis
,
19:57
Re: [PATCH v2] target/riscv: Add support for machine specific pmu's events
,
Richard Henderson
,
14:50
[RFC PATCH v3 2/2] tests/qtest: QTest example for RISC-V CSR register
,
Ivan Klokov
,
11:36
[RFC PATCH v3 1/2] target/riscv: Add RISC-V CSR qtest support
,
Ivan Klokov
,
11:36
[RFC PATCH v3 0/2] Support RISC-V CSR read/write in Qtest environment
,
Ivan Klokov
,
11:36
Re: [PATCH v3 14/15] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Sunil V L
,
11:18
Re: [RFC PATCH v4 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
,
Max Chou
,
11:14
[PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Sunil V L
,
11:10
[PATCH v4 15/16] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Sunil V L
,
11:10
[PATCH v4 14/16] tests/qtest/bios-tables-test: Add empty ACPI data files for RISC-V
,
Sunil V L
,
11:10
[PATCH v4 13/16] tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V
,
Sunil V L
,
11:10
[PATCH v4 12/16] pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs
,
Sunil V L
,
11:10
[PATCH v4 11/16] meson.build: Add RISC-V to the edk2-target list
,
Sunil V L
,
11:09
[PATCH v4 10/16] tests/data/acpi/virt: Move ARM64 ACPI tables under aarch64/${machine} path
,
Sunil V L
,
11:09
[PATCH v4 09/16] tests/data/acpi: Move x86 ACPI tables under x86/${machine} path
,
Sunil V L
,
11:09
[PATCH v4 08/16] tests/qtest/bios-tables-test.c: Set "arch" for x86 tests
,
Sunil V L
,
11:09
[PATCH v4 07/16] tests/qtest/bios-tables-test.c: Set "arch" for aarch64 tests
,
Sunil V L
,
11:09
[PATCH v4 06/16] tests/qtest/bios-tables-test.c: Add support for arch in path
,
Sunil V L
,
11:09
[PATCH v4 05/16] qtest: bios-tables-test: Rename aarch64 tests with aarch64 in them
,
Sunil V L
,
11:09
[PATCH v4 04/16] tests/data/uefi-boot-images: Add RISC-V ISO image
,
Sunil V L
,
11:09
[PATCH v4 03/16] uefi-test-tools: Add support for python based build script
,
Sunil V L
,
11:09
[PATCH v4 02/16] uefi-test-tools/UefiTestToolsPkg: Add RISC-V support
,
Sunil V L
,
11:09
[PATCH v4 01/16] hw/riscv/virt.c: Make block devices default to virtio
,
Sunil V L
,
11:09
[PATCH v4 00/16] Add support for RISC-V ACPI tests
,
Sunil V L
,
11:08
[PATCH v8] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI
,
Alexei Filippov
,
11:03
[PATCH v2] target/riscv: Add support for machine specific pmu's events
,
Alexei Filippov
,
10:46
[PATCH] target/riscv: Add support for machine specific pmu's events
,
Alexei Filippov
,
10:41
Re: [PATCH v3 14/15] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Igor Mammedov
,
10:07
Re: [PATCH v3 14/15] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Sunil V L
,
08:29
Re: [PATCH v3 14/15] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Igor Mammedov
,
08:06
[PATCH v3 6/6] target/riscv: Remove extension auto-update check statements
,
frank . chang
,
07:47
[PATCH v3 5/6] target/riscv: Add Zc extension implied rule
,
frank . chang
,
07:47
[PATCH v3 3/6] target/riscv: Add MISA extension implied rules
,
frank . chang
,
07:47
[PATCH v3 4/6] target/riscv: Add multi extension implied rules
,
frank . chang
,
07:47
[PATCH v3 2/6] target/riscv: Introduce extension implied rule helpers
,
frank . chang
,
07:47
[PATCH v3 0/6] Introduce extension implied rules
,
frank . chang
,
07:46
[PATCH v3 1/6] target/riscv: Introduce extension implied rules definition
,
frank . chang
,
07:46
Re: [PATCH v3 14/15] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Igor Mammedov
,
07:20
Re: [PATCH v3 09/15] tests/data/acpi/virt: Move ARM64 ACPI tables under aarch64/${machine} path
,
Igor Mammedov
,
06:49
Re: [PATCH v3 08/15] tests/data/acpi: Move x86 ACPI tables under x86/${machine} path
,
Igor Mammedov
,
06:49
Re: [PATCH v3 07/15] tests/qtest/bios-tables-test.c: Set "arch" for x86 tests
,
Igor Mammedov
,
06:49
Re: [PATCH v3 06/15] tests/qtest/bios-tables-test.c: Set "arch" for aarch64 tests
,
Igor Mammedov
,
06:48
Re: [PATCH v3 05/15] tests/qtest/bios-tables-test.c: Add support for arch in path
,
Igor Mammedov
,
06:48
Re: [PATCH v2 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.
,
Jason Chien
,
05:48
Re: [PATCH v2 5/6] target/riscv: Add CTR sctrclr instruction.
,
Jason Chien
,
05:06
Re: [PATCH v3 02/15] uefi-test-tools: Add support for python based build script
,
Igor Mammedov
,
04:42
Re: [PATCH v3 01/15] uefi-test-tools/UefiTestToolsPkg: Add RISC-V support
,
Igor Mammedov
,
04:42
Re: [PATCH v2 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.
,
Jason Chien
,
04:28
Re: [PATCH v2 1/6] target/riscv: Remove obsolete sfence.vm instruction
,
Jason Chien
,
03:59
June 24, 2024
Re: [PATCH v2] target/riscv: fix instructions count handling in icount mode
,
Alistair Francis
,
21:47
[PATCH v4 14/14] docs/specs: add riscv-iommu
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 13/14] qtest/riscv-iommu-test: add init queues test
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 12/14] hw/riscv/riscv-iommu: Add another irq for mrif notifications
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 11/14] hw/riscv/riscv-iommu: add DBG support
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 10/14] hw/riscv/riscv-iommu: add ATS support
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 09/14] hw/riscv/riscv-iommu: add s-stage and g-stage support
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 08/14] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 07/14] test/qtest: add riscv-iommu-pci tests
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 06/14] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 05/14] hw/riscv: add riscv-iommu-pci reference device
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 04/14] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation
,
Daniel Henrique Barboza
,
16:19
[PATCH v4 02/14] hw/riscv: add riscv-iommu-bits.h
,
Daniel Henrique Barboza
,
16:18
[PATCH v4 01/14] exec/memtxattr: add process identifier to the transaction attributes
,
Daniel Henrique Barboza
,
16:18
[PATCH v4 00/14] riscv: QEMU RISC-V IOMMU Support
,
Daniel Henrique Barboza
,
16:18
Re: [PATCH v3 02/15] uefi-test-tools: Add support for python based build script
,
Gerd Hoffmann
,
04:04
Re: [RFC PATCH v4 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions
,
Max Chou
,
02:50
Re: [PATCH v3 06/15] tests/qtest/bios-tables-test.c: Set "arch" for aarch64 tests
,
Alistair Francis
,
02:05
Re: [PATCH v3 05/15] tests/qtest/bios-tables-test.c: Add support for arch in path
,
Alistair Francis
,
02:03
June 23, 2024
Re: [PATCH v7 2/2] hw/riscv/virt: Add IOPMP support
,
Ethan Chen
,
21:47
June 21, 2024
[PATCH v3 15/15] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Sunil V L
,
08:01
[PATCH v3 14/15] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Sunil V L
,
08:01
[PATCH v3 13/15] tests/qtest/bios-tables-test: Add empty ACPI data files for RISC-V
,
Sunil V L
,
08:01
[PATCH v3 12/15] tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V
,
Sunil V L
,
08:00
[PATCH v3 11/15] pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs
,
Sunil V L
,
08:00
[PATCH v3 10/15] meson.build: Add RISC-V to the edk2-target list
,
Sunil V L
,
08:00
[PATCH v3 09/15] tests/data/acpi/virt: Move ARM64 ACPI tables under aarch64/${machine} path
,
Sunil V L
,
08:00
[PATCH v3 08/15] tests/data/acpi: Move x86 ACPI tables under x86/${machine} path
,
Sunil V L
,
08:00
[PATCH v3 07/15] tests/qtest/bios-tables-test.c: Set "arch" for x86 tests
,
Sunil V L
,
08:00
[PATCH v3 06/15] tests/qtest/bios-tables-test.c: Set "arch" for aarch64 tests
,
Sunil V L
,
07:59
[PATCH v3 05/15] tests/qtest/bios-tables-test.c: Add support for arch in path
,
Sunil V L
,
07:59
[PATCH v3 04/15] qtest: bios-tables-test: Rename aarch64 tests with aarch64 in them
,
Sunil V L
,
07:59
[PATCH v3 03/15] tests/data/uefi-boot-images: Add RISC-V ISO image
,
Sunil V L
,
07:59
[PATCH v3 01/15] uefi-test-tools/UefiTestToolsPkg: Add RISC-V support
,
Sunil V L
,
07:59
[PATCH v3 02/15] uefi-test-tools: Add support for python based build script
,
Sunil V L
,
07:59
[PATCH v3 00/15] Add support for RISC-V ACPI tests
,
Sunil V L
,
07:59
Re: [PATCH v3 09/13] hw/riscv/riscv-iommu: add s-stage and g-stage support
,
Daniel Henrique Barboza
,
07:59
Re: [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers
,
Frank Chang
,
02:51
Re: [PATCH v7 2/2] hw/riscv/virt: Add IOPMP support
,
Alistair Francis
,
01:54
Re: [PATCH] target/riscv: Fix froundnx.h nanbox check
,
Alistair Francis
,
00:44
Re: [PATCH] target/riscv: Fix froundnx.h nanbox check
,
Richard Henderson
,
00:22
Re: [PATCH] target/riscv: Fix froundnx.h nanbox check
,
Alistair Francis
,
00:21
Re: [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers
,
Alistair Francis
,
00:15
June 20, 2024
Re: [PATCH] hw/riscv/virt.c: Make block devices default to virtio
,
Alistair Francis
,
22:09
Re: [PATCH] hw/riscv/virt.c: Make block devices default to virtio
,
Alistair Francis
,
21:18
Re: [PATCH v2 6/6] target/riscv: Remove extension auto-update check statements
,
Daniel Henrique Barboza
,
15:54
Re: [PATCH v2 5/6] target/riscv: Add Zc extension implied rule
,
Daniel Henrique Barboza
,
15:54
Re: [PATCH v2 4/6] target/riscv: Add standard extension implied rules
,
Daniel Henrique Barboza
,
15:53
Re: [PATCH v2 3/6] target/riscv: Add MISA implied rules
,
Daniel Henrique Barboza
,
15:53
Re: [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers
,
Daniel Henrique Barboza
,
15:52
Re: [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition
,
Daniel Henrique Barboza
,
15:51
Re: Is there a way to check values of registers before and after running a program on qemu-system-risc64v?
,
Shobhit
,
12:17
Re: [RFC PATCH v4 1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb
,
Alex Bennée
,
10:27
Re: [PATCH v2 06/12] tests/data/acpi/virt: Move ACPI tables under aarch64
,
Igor Mammedov
,
09:53
Re: [PATCH] hw/riscv/virt.c: Make block devices default to virtio
,
Daniel Henrique Barboza
,
07:23
Re: [RFC PATCH v4 1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb
,
Frank Chang
,
03:50
[PATCH] hw/riscv/virt.c: Make block devices default to virtio
,
Sunil V L
,
02:47
Re: [RFC PATCH v4 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance
,
Richard Henderson
,
00:44
Re: [RFC PATCH v4 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
,
Richard Henderson
,
00:41
Re: [RFC PATCH v4 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions
,
Richard Henderson
,
00:38
Re: [RFC PATCH v4 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
,
Richard Henderson
,
00:29
June 19, 2024
Re: [RFC PATCH v4 1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb
,
Richard Henderson
,
22:48
Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
,
Ethan Chen
,
22:30
Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
,
Ethan Chen
,
22:28
Re: [PATCH v2] target/riscv: fix instructions count handling in icount mode
,
Atish Kumar Patra
,
15:56
Re: Is there a way to check values of registers before and after running a program on qemu-system-risc64v?
,
Deepak Gupta
,
14:20
Re: [PATCH v2 11/12] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Sunil V L
,
14:06
Re: [PATCH v2 06/12] tests/data/acpi/virt: Move ACPI tables under aarch64
,
Sunil V L
,
14:00
Re: Is there a way to check values of registers before and after running a program on qemu-system-risc64v?
,
Shobhit
,
12:57
Re: Is there a way to check values of registers before and after running a program on qemu-system-risc64v?
,
Himanshu Chauhan
,
12:16
Re: Is there a way to check values of registers before and after running a program on qemu-system-risc64v?
,
Shobhit
,
11:51
[PATCH v2 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.
,
Rajnesh Kanwal
,
11:27
[PATCH v2 5/6] target/riscv: Add CTR sctrclr instruction.
,
Rajnesh Kanwal
,
11:27
[PATCH v2 4/6] target/riscv: Add support to record CTR entries.
,
Rajnesh Kanwal
,
11:27
[PATCH v2 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.
,
Rajnesh Kanwal
,
11:27
[PATCH v2 2/6] target/riscv: Add Control Transfer Records CSR definitions.
,
Rajnesh Kanwal
,
11:27
[PATCH v2 1/6] target/riscv: Remove obsolete sfence.vm instruction
,
Rajnesh Kanwal
,
11:27
[PATCH v2 0/6] target/riscv: Add support for Control Transfer Records Ext.
,
Rajnesh Kanwal
,
11:27
Re: [PATCH v2 12/12] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Igor Mammedov
,
07:07
Re: [PATCH v2 11/12] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Igor Mammedov
,
06:13
Re: [PATCH v2 10/12] tests/qtest/bios-tables-test: Add empty ACPI data files for RISC-V
,
Igor Mammedov
,
05:44
Re: [PATCH v2 09/12] tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V
,
Igor Mammedov
,
05:43
Re: [PATCH v2 08/12] pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs
,
Igor Mammedov
,
05:35
Re: [PATCH v2 06/12] tests/data/acpi/virt: Move ACPI tables under aarch64
,
Michael S. Tsirkin
,
05:21
Re: [PATCH v2 05/12] tests/qtest/bios-tables-test.c: Add support for arch in path
,
Igor Mammedov
,
05:21
Re: [PATCH v2 07/12] meson.build: Add RISC-V to the edk2-target list
,
Igor Mammedov
,
05:19
Re: [PATCH v2 06/12] tests/data/acpi/virt: Move ACPI tables under aarch64
,
Igor Mammedov
,
05:17
Re: Is there a way to check values of registers before and after running a program on qemu-system-risc64v?
,
address@hidden
,
00:42
June 18, 2024
Re: Is there a way to check values of registers before and after running a program on qemu-system-risc64v?
,
Deepak Gupta
,
12:55
Is there a way to check values of registers before and after running a program on qemu-system-risc64v?
,
Shobhit
,
12:50
Re: [PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation
,
Jason Chien
,
11:15
Re: [PATCH v2 04/12] qtest: bios-tables-test: Rename aarch64 tests with aarch64 in them
,
Igor Mammedov
,
08:34
[PATCH v2] target/riscv: fix instructions count handling in icount mode
,
Clément Léger
,
07:27
Re: [PATCH v3 2/3] hw/dma: Add a trace log for a description loading failure
,
Philippe Mathieu-Daudé
,
06:54
Re: [PATCH v3 09/13] hw/riscv/riscv-iommu: add s-stage and g-stage support
,
Jason Chien
,
06:30
Re: [PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation
,
Jason Chien
,
06:07
Re: [RFC PATCH v2 1/2] Add RISC-V CSR qtest support
,
Thomas Huth
,
03:47
[RFC PATCH v2 1/2] Add RISC-V CSR qtest support
,
Ivan Klokov
,
02:45
[RFC PATCH v2 2/2] QTest example for RISC-V CSR register
,
Ivan Klokov
,
02:45
[RFC PATCH v2 0/2] Support RISC-V CSR read/write in Qtest environment
,
Ivan Klokov
,
02:45
June 17, 2024
Re: [PATCH v3] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
,
Zhenyu Zhang
,
09:36
Re: Can I utilize the RISC-V vector extension with QEMU?
,
Daniel Henrique Barboza
,
09:12
Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
,
Stefan Weil
,
08:09
Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
,
LIU Zhiwei
,
07:30
Re: [PATCH v3] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
,
Philippe Mathieu-Daudé
,
05:36
June 15, 2024
[PATCH v2 6/6] target/riscv: Remove extension auto-update check statements
,
frank . chang
,
22:47
[PATCH v2 4/6] target/riscv: Add standard extension implied rules
,
frank . chang
,
22:47
[PATCH v2 5/6] target/riscv: Add Zc extension implied rule
,
frank . chang
,
22:47
[PATCH v2 3/6] target/riscv: Add MISA implied rules
,
frank . chang
,
22:47
[PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers
,
frank . chang
,
22:47
[PATCH v2 1/6] target/riscv: Introduce extension implied rules definition
,
frank . chang
,
22:47
[PATCH v2 0/6] Introduce extension implied rules
,
frank . chang
,
22:47
June 14, 2024
Re: [RFC PATCH 01/16] accel/tcg: Store section pointer in CPUTLBEntryFull
,
LIU Zhiwei
,
09:29
Re: [PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support
,
LIU Zhiwei
,
09:24
Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
,
LIU Zhiwei
,
09:03
June 13, 2024
Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
,
Ethan Chen
,
21:47
Can I utilize the RISC-V vector extension with QEMU?
,
bithamr
,
20:41
[RFC PATCH v4 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance
,
Max Chou
,
13:51
[RFC PATCH v4 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions
,
Max Chou
,
13:51
[RFC PATCH v4 3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store
,
Max Chou
,
13:51
[RFC PATCH v4 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
,
Max Chou
,
13:51
[RFC PATCH v4 1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb
,
Max Chou
,
13:51
[RFC PATCH v4 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions
,
Max Chou
,
13:51
Re: [RFC PATCH v3 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions
,
Daniel Henrique Barboza
,
11:43
[RFC PATCH v3 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance
,
Max Chou
,
10:19
[RFC PATCH v3 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
,
Max Chou
,
10:19
[RFC PATCH v3 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions
,
Max Chou
,
10:19
[RFC PATCH v3 3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store
,
Max Chou
,
10:19
[RFC PATCH v3 1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb
,
Max Chou
,
10:19
[RFC PATCH v3 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions
,
Max Chou
,
10:19
Re: [RFC PATCH 01/16] accel/tcg: Store section pointer in CPUTLBEntryFull
,
Jim Shu
,
06:38
Re: [PATCH 2/2] QTest example for RISC-V CSR register
,
Thomas Huth
,
06:14
[PATCH 1/2] Add RISC-V CSR qtest support
,
Ivan Klokov
,
05:56
[PATCH 2/2] QTest example for RISC-V CSR register
,
Ivan Klokov
,
05:56
[RFC PATCH 0/2] Support RISC-V CSR read/write in Qtest environment
,
Ivan Klokov
,
05:56
Re: [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU
,
Jim Shu
,
05:52
Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
,
LIU Zhiwei
,
05:27
Re: [RFC PATCH 01/16] accel/tcg: Store section pointer in CPUTLBEntryFull
,
LIU Zhiwei
,
02:23
Re: [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU
,
Ethan Chen
,
01:40
June 12, 2024
[PATCH v3 3/3] hw/net: Fix the transmission return size
,
Fea.Wang
,
21:30
[PATCH v3 2/3] hw/dma: Add a trace log for a description loading failure
,
Fea.Wang
,
21:30
[PATCH v3 1/3] hw/dma: Enhance error handling in loading description
,
Fea.Wang
,
21:30
[PATCH v3 0/3] hw/dma: Add error handling for loading descriptions failing
,
Fea.Wang
,
21:29
Re: [PATCH v3] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
,
Robin Murphy
,
16:20
Re: [PATCH v3] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
,
Philippe Mathieu-Daudé
,
08:50
Re: [PATCH v3] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
,
Peter Maydell
,
08:48
Re: [PATCH v3] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
,
Philippe Mathieu-Daudé
,
08:33
Re: [PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support
,
Daniel Henrique Barboza
,
08:10
Re: [PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation
,
Daniel Henrique Barboza
,
05:53
[RFC PATCH 16/16] hw/riscv: virt: Add WorldGuard support
,
Jim Shu
,
04:16
[RFC PATCH 15/16] hw/misc: riscv_wgchecker: Check the slot settings in translate
,
Jim Shu
,
04:16
[RFC PATCH 14/16] hw/misc: riscv_wgchecker: Implement correct block-access behavior
,
Jim Shu
,
04:16
[RFC PATCH 13/16] hw/misc: riscv_wgchecker: Implement wgchecker slot registers
,
Jim Shu
,
04:15
[RFC PATCH 12/16] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker
,
Jim Shu
,
04:15
[RFC PATCH 11/16] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU
,
Jim Shu
,
04:15
[RFC PATCH 09/16] target/riscv: Implement WorldGuard CSRs
,
Jim Shu
,
04:15
[RFC PATCH 10/16] target/riscv: Add WID to MemTxAttrs of CPU memory transactions
,
Jim Shu
,
04:15
[RFC PATCH 08/16] target/riscv: Allow global WG config to set WG CPU callbacks
,
Jim Shu
,
04:15
[RFC PATCH 07/16] target/riscv: Add defines for WorldGuard CSRs
,
Jim Shu
,
04:15
[RFC PATCH 06/16] target/riscv: Add hard-coded CPU state of WG extension
,
Jim Shu
,
04:15
[RFC PATCH 05/16] target/riscv: Add CPU options of WorldGuard CPU extension
,
Jim Shu
,
04:15
[RFC PATCH 04/16] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config
,
Jim Shu
,
04:15
[RFC PATCH 03/16] exec: Add RISC-V WorldGuard WID to MemTxAttrs
,
Jim Shu
,
04:14
[RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU
,
Jim Shu
,
04:14
[RFC PATCH 01/16] accel/tcg: Store section pointer in CPUTLBEntryFull
,
Jim Shu
,
04:14
[RFC PATCH 00/16] Implements RISC-V WorldGuard extension v0.4
,
Jim Shu
,
04:14
Re: [PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support
,
LIU Zhiwei
,
03:51
June 11, 2024
[PATCH v7 2/2] hw/riscv/virt: Add IOPMP support
,
Ethan Chen
,
23:23
[PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
,
Ethan Chen
,
23:23
[PATCH v7 0/2] Support RISC-V IOPMP
,
Ethan Chen
,
23:23
Re: [PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.
,
Jason Chien
,
23:13
Re: qemu-riscv32 usermode still broken?
,
Alistair Francis
,
21:27
Re: [PATCH RESEND 2/6] target/riscv: Introduce extension implied rule helpers
,
Frank Chang
,
21:21
Re: [PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation
,
Jason Chien
,
12:15
Re: [PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support
,
Daniel Henrique Barboza
,
06:13
Re: [PATCH v3 0/5] semihosting: Restrict to TCG
,
Alex Bennée
,
06:07
Re: qemu-riscv32 usermode still broken?
,
Andreas K. Huettel
,
04:58
Re: qemu-riscv32 usermode still broken?
,
Alistair Francis
,
00:44
June 10, 2024
Re: [PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition
,
Frank Chang
,
21:56
Re: [PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support
,
LIU Zhiwei
,
21:53
Re: [PATCH RESEND 4/6] target/riscv: Add standard extension implied rules
,
Alistair Francis
,
21:45
Re: [PATCH RESEND 3/6] target/riscv: Add MISA implied rules
,
Alistair Francis
,
21:42
Re: [PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition
,
Alistair Francis
,
21:35
Re: [PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support
,
Alistair Francis
,
20:18
Re: [PATCH v3 4/5] target/riscv: Restrict semihosting to TCG
,
Alistair Francis
,
20:17
Re: [PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support
,
Daniel Henrique Barboza
,
15:16
Re: [PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support
,
Andrew Jones
,
14:32
Re: [PATCH v3 2/5] target/xtensa: Restrict semihosting to TCG
,
Max Filippov
,
14:28
[PATCH v3 5/5] semihosting: Restrict to TCG
,
Philippe Mathieu-Daudé
,
10:58
[PATCH v3 4/5] target/riscv: Restrict semihosting to TCG
,
Philippe Mathieu-Daudé
,
10:58
[PATCH v3 3/5] target/mips: Restrict semihosting to TCG
,
Philippe Mathieu-Daudé
,
10:58
[PATCH v3 2/5] target/xtensa: Restrict semihosting to TCG
,
Philippe Mathieu-Daudé
,
10:58
[PATCH v3 1/5] target/m68k: Restrict semihosting to TCG
,
Philippe Mathieu-Daudé
,
10:58
[PATCH v3 0/5] semihosting: Restrict to TCG
,
Philippe Mathieu-Daudé
,
10:58
Re: [PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.
,
Rajnesh Kanwal
,
10:12
June 09, 2024
Re: [PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support
,
Alistair Francis
,
20:35
Re: [PATCH v3 11/13] hw/riscv/riscv-iommu: add DBG support
,
Frank Chang
,
05:10
Re: [PATCH v3 10/13] hw/riscv/riscv-iommu: add ATS support
,
Frank Chang
,
05:06
Re: [PATCH v3 05/13] hw/riscv: add riscv-iommu-pci reference device
,
Frank Chang
,
04:53
[PATCH] target/riscv: Fix froundnx.h nanbox check
,
Branislav Brzak
,
01:31
June 07, 2024
Re: [PATCH] target/riscv: support atomic instruction fetch (Ziccif)
,
Richard Henderson
,
09:39
[PATCH] target/riscv: support atomic instruction fetch (Ziccif)
,
Jim Shu
,
06:14
Re: [PATCH v3 08/13] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
,
Daniel Henrique Barboza
,
04:30
Re: [PATCH v4 0/6] target/riscv: Support RISC-V privilege 1.13 spec
,
Alistair Francis
,
01:05
June 06, 2024
Re: [PATCH v4 6/6] target/riscv: Support the version for ss1p13
,
Alistair Francis
,
21:13
Re: [PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation
,
Daniel Henrique Barboza
,
15:46
Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.
,
Beeman Strong
,
14:36
[PATCH v4 6/6] target/riscv: Support the version for ss1p13
,
Fea.Wang
,
09:50
[PATCH v4 5/6] target/riscv: Reserve exception codes for sw-check and hw-err
,
Fea.Wang
,
09:49
[PATCH v4 4/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
,
Fea.Wang
,
09:49
[PATCH v4 3/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0
,
Fea.Wang
,
09:49
[PATCH v4 2/6] target/riscv: Define macros and variables for ss1p13
,
Fea.Wang
,
09:49
[PATCH v4 1/6] target/riscv: Reuse the conversion function of priv_spec
,
Fea.Wang
,
09:49
[PATCH v4 0/6] target/riscv: Support RISC-V privilege 1.13 spec
,
Fea.Wang
,
09:49
Re: [PATCH v3 3/6] target/riscv: Support the version for ss1p13
,
Fea Wang
,
09:43
Re: [PATCH 3/3] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Sunil V L
,
05:50
June 05, 2024
Re: [PATCH v4 0/3] target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V
,
Alistair Francis
,
21:57
[PATCH v4 2/3] target/riscv/kvm: handle the exit with debug reason
,
Chao Du
,
21:50
[PATCH v4 3/3] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG
,
Chao Du
,
21:50
[PATCH v4 0/3] target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V
,
Chao Du
,
21:50
[PATCH v4 1/3] target/riscv/kvm: add software breakpoints support
,
Chao Du
,
21:50
Re: [PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0
,
Alistair Francis
,
19:59
Re: [PATCH v3 3/6] target/riscv: Support the version for ss1p13
,
Alistair Francis
,
19:58
Re: [PATCH v3 2/6] target/riscv: Define macros and variables for ss1p13
,
Alistair Francis
,
19:53
Re: [PATCH v3 0/3] target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V
,
Alistair Francis
,
19:52
Re: [PATCH v3 02/13] hw/riscv: add riscv-iommu-bits.h
,
Daniel Henrique Barboza
,
18:21
Re: [PATCH v3 08/13] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
,
Tomasz Jeznach
,
13:35
Re: [PATCH 5/6] target/riscv: Add CTR sctrclr instruction.
,
Beeman Strong
,
11:17
Re: [PATCH 3/3] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Igor Mammedov
,
10:48
Re: [PATCH RFC 4/8] target/riscv: Support generic CSR indirect access
,
Jason Chien
,
07:49
Re: [PATCH 1/3] gpex-acpi: Support PCI link devices outside the host bridge
,
Sunil V L
,
07:43
Re: [PATCH 1/3] gpex-acpi: Support PCI link devices outside the host bridge
,
Michael S. Tsirkin
,
04:23
Re: [PATCH RFC 2/8] target/riscv: Decouple AIA processing from xiselect and xireg
,
Jason Chien
,
04:17
[PATCH RESEND 0/6] Introduce extension implied rules
,
Jerry Zhang Jian
,
03:49
Re: [PATCH 0/6] Introduce extension implied rules
,
Frank Chang
,
02:54
[PATCH RESEND 6/6] target/riscv: Remove extension auto-update check statements
,
frank . chang
,
02:32
[PATCH RESEND 5/6] target/riscv: Add Zc extension implied rule
,
frank . chang
,
02:32
[PATCH RESEND 4/6] target/riscv: Add standard extension implied rules
,
frank . chang
,
02:32
[PATCH RESEND 3/6] target/riscv: Add MISA implied rules
,
frank . chang
,
02:32
[PATCH RESEND 2/6] target/riscv: Introduce extension implied rule helpers
,
frank . chang
,
02:32
[PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition
,
frank . chang
,
02:32
[PATCH RESEND 0/6] Introduce extension implied rules
,
frank . chang
,
02:32
Re: [PATCH 2/6] target/riscv: Introduce extension implied rule helpers
,
Frank Chang
,
02:31
Re: [PATCH 5/6] target/riscv: Add CTR sctrclr instruction.
,
Jason Chien
,
02:28
June 04, 2024
Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.
,
Beeman Strong
,
23:41
Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.
,
Jason Chien
,
23:34
[PATCH v3 2/3] target/riscv/kvm: handle the exit with debug reason
,
Chao Du
,
23:00
[PATCH v3 3/3] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG
,
Chao Du
,
23:00
[PATCH v3 1/3] target/riscv/kvm: add software breakpoints support
,
Chao Du
,
23:00
[PATCH v3 0/3] target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V
,
Chao Du
,
23:00
Re: [PATCH 1/6] target/riscv: Remove obsolete sfence.vm instruction
,
Alistair Francis
,
20:46
Re: [PATCH v2 0/8] hw/riscv/virt.c: aplic/imsic DT fixes
,
Alistair Francis
,
20:44
Re: [PATCH v2 8/8] hw/riscv/virt.c: imsics DT: add '#msi-cells'
,
Alistair Francis
,
20:36
Re: [PATCH v2 7/8] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible'
,
Alistair Francis
,
20:36
Re: [PATCH v2 6/8] hw/riscv/virt.c: change imsic nodename to 'interrupt-controller'
,
Alistair Francis
,
20:36
Re: [PATCH v2 5/8] hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation'
,
Alistair Francis
,
20:35
Re: [PATCH v2 4/8] hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible'
,
Alistair Francis
,
20:31
Re: [PATCH v2 3/8] hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller'
,
Alistair Francis
,
20:30
Re: [PATCH v2 2/8] hw/riscv/virt.c: add aplic nodename helper
,
Alistair Francis
,
20:19
Re: [PATCH v2 1/8] hw/riscv/virt.c: add address-cells in create_fdt_one_aplic()
,
Alistair Francis
,
20:07
Re: [PATCH RESEND v2 3/3] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG
,
Alistair Francis
,
19:14
Re: [PATCH RESEND v2 2/3] target/riscv/kvm: handle the exit with debug reason
,
Alistair Francis
,
19:13
Re: [PATCH RESEND v2 1/3] target/riscv/kvm: add software breakpoints support
,
Alistair Francis
,
19:12
Re: [PATCH 3/3] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Alistair Francis
,
19:10
Re: [PATCH 2/3] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
,
Alistair Francis
,
19:09
Re: [PATCH 1/3] gpex-acpi: Support PCI link devices outside the host bridge
,
Alistair Francis
,
19:07
Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.
,
Beeman Strong
,
18:33
Re: [PATCH 5/6] target/riscv: Add CTR sctrclr instruction.
,
Beeman Strong
,
15:54
Re: [PATCH 5/6] target/riscv: Add CTR sctrclr instruction.
,
Jason Chien
,
13:20
Re: [PATCH 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.
,
Jason Chien
,
13:07
Re: [PATCH 4/6] target/riscv: Add support to record CTR entries.
,
Jason Chien
,
12:30
Re: [RFC v2 3/7] hw/core: Add cache topology options in -smp
,
Zhao Liu
,
11:53
Re: [RFC v2 0/7] Introduce SMP Cache Topology
,
Zhao Liu
,
11:16
Re: [PATCH] target/riscv: rvzicbo: Fixup CBO extension register calculation
,
Philippe Mathieu-Daudé
,
07:37
Re: [PATCH v2 0/8] hw/riscv/virt.c: aplic/imsic DT fixes
,
Conor Dooley
,
07:29
Re: [PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.
,
Jason Chien
,
06:14
Re: [RFC v2 3/7] hw/core: Add cache topology options in -smp
,
Daniel P . Berrangé
,
05:32
Re: [RFC v2 0/7] Introduce SMP Cache Topology
,
Daniel P . Berrangé
,
05:29
[PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
,
Yu-Ming Chang
,
05:15
Re: [RFC v2 3/7] hw/core: Add cache topology options in -smp
,
Markus Armbruster
,
04:55
Re: [RFC v2 1/7] hw/core: Make CPU topology enumeration arch-agnostic
,
Zhao Liu
,
04:51
Re: [RFC v2 1/7] hw/core: Make CPU topology enumeration arch-agnostic
,
Markus Armbruster
,
04:47
Re: [RFC v2 1/7] hw/core: Make CPU topology enumeration arch-agnostic
,
Markus Armbruster
,
04:44
Re: [PATCH] target/riscv: rvzicbo: Fixup CBO extension register calculation
,
Philippe Mathieu-Daudé
,
04:32
Re: [RFC v2 1/7] hw/core: Make CPU topology enumeration arch-agnostic
,
Zhao Liu
,
04:24
Re: [RFC v2 1/7] hw/core: Make CPU topology enumeration arch-agnostic
,
Zhao Liu
,
04:18
Re: [PATCH] target/riscv: Use get_address() to get address with Zicbom extensions
,
Philippe Mathieu-Daudé
,
04:08
Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.
,
Jason Chien
,
03:29
Re: [PATCH v2 00/12] Add support for RISC-V ACPI tests
,
Michael S. Tsirkin
,
03:05
Re: [PATCH 4/4] hw/net: Fix the transmission return size
,
Frank Chang
,
03:01
Re: [PATCH 3/4] hw/dma: Add a trace log for a description loading failure
,
Frank Chang
,
03:01
Re: [PATCH 2/4] hw/dma: Break the loop when loading descriptions fails
,
Frank Chang
,
03:01
Re: [PATCH 1/4] hw/dma: Enhance error handling in loading description
,
Frank Chang
,
03:00
Re: [PATCH 4/4] hw/net: Fix the transmission return size
,
Fea Wang
,
02:57
Re: [PATCH 2/4] hw/dma: Break the loop when loading descriptions fails
,
Fea Wang
,
02:52
Re: [PATCH v5 0/4] RISC-V: Modularize common match conditions for trigger
,
Alistair Francis
,
02:43
Re: [PATCH 1/4] hw/dma: Enhance error handling in loading description
,
Fea Wang
,
02:41
[PATCH v3 6/6] target/riscv: Reserve exception codes for sw-check and hw-err
,
Fea.Wang
,
02:22
[PATCH v3 5/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
,
Fea.Wang
,
02:22
[PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0
,
Fea.Wang
,
02:22
[PATCH v3 3/6] target/riscv: Support the version for ss1p13
,
Fea.Wang
,
02:22
[PATCH v3 2/6] target/riscv: Define macros and variables for ss1p13
,
Fea.Wang
,
02:22
[PATCH v3 1/6] target/riscv: Reuse the conversion function of priv_spec
,
Fea.Wang
,
02:22
[PATCH v3 0/6] target/riscv: Support RISC-V privilege 1.13 spec
,
Fea.Wang
,
02:22
[PATCH v5 4/4] target/riscv: Apply modularized matching conditions for icount trigger
,
Alvin Chang
,
00:42
[PATCH v5 3/4] target/riscv: Apply modularized matching conditions for watchpoint
,
Alvin Chang
,
00:41
[PATCH v5 2/4] target/riscv: Apply modularized matching conditions for breakpoint
,
Alvin Chang
,
00:41
[PATCH v5 1/4] target/riscv: Add functions for common matching conditions of trigger
,
Alvin Chang
,
00:41
[PATCH v5 0/4] RISC-V: Modularize common match conditions for trigger
,
Alvin Chang
,
00:41
RE: [PATCH v4 0/4] RISC-V: Modularize common match conditions for trigger
,
張哲嘉
,
00:24
June 03, 2024
Re: [RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0
,
Fea Wang
,
23:56
Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
,
Alistair Francis
,
23:42
Re: [RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13
,
Fea Wang
,
23:40
Re: [PATCH v2] target/riscv: zvbb implies zvkb
,
Alistair Francis
,
23:36
Re: [PATCH v2 00/12] Add support for RISC-V ACPI tests
,
Alistair Francis
,
23:30
Re: [PATCH v2 12/12] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Alistair Francis
,
23:28
Re: [PATCH v2 11/12] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Alistair Francis
,
23:28
Re: [PATCH v2 10/12] tests/qtest/bios-tables-test: Add empty ACPI data files for RISC-V
,
Alistair Francis
,
23:27
Re: [PATCH v2 01/12] uefi-test-tools/UefiTestToolsPkg: Add RISC-V support
,
Alistair Francis
,
23:23
Re: [PATCH 6/6] disas/riscv: Support zabha disassemble
,
Alistair Francis
,
23:18
Re: [PATCH 4/6] target/riscv: Add amocas.[b|h] for Zabha
,
Alistair Francis
,
23:17
Re: [PATCH 3/6] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
,
Alistair Francis
,
23:15
Re: [PATCH 2/6] target/riscv: Add AMO instructions for Zabha
,
Alistair Francis
,
23:10
Re: [PATCH 1/6] target/riscv: Move gen_amo before implement Zabha
,
Alistair Francis
,
22:26
Re: [PATCH 4/4] disas/riscv: Support zcmop disassemble
,
Alistair Francis
,
22:24
Re: [PATCH 3/4] target/riscv: Add zcmop extension
,
Alistair Francis
,
22:23
Re: [PATCH 2/4] disas/riscv: Support zimop disassemble
,
Alistair Francis
,
22:21
Re: [PATCH 1/4] target/riscv: Add zimop extension
,
Alistair Francis
,
22:20
Re: [PATCH v2 0/2] target/riscv: Minor fixes and improvements for Virtual IRQs
,
Alistair Francis
,
22:16
Re: [PATCH v4 0/4] RISC-V: Modularize common match conditions for trigger
,
Alistair Francis
,
21:58
Re: [PATCH v2 2/2] target/riscv: Move Guest irqs out of the core local irqs range.
,
Alistair Francis
,
21:57
Re: [PATCH v2 1/2] target/riscv: Extend virtual irq csrs masks to be 64 bit wide.
,
Alistair Francis
,
21:55
Re: [PATCH v3 1/2] target/riscv/csr.c: Add functional of hvictl CSR
,
Alistair Francis
,
21:10
Re: [PATCH] Fix incorrect disassembly format for certain RISC-V instructions
,
Alistair Francis
,
21:05
Re: [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations
,
Richard Henderson
,
20:58
Re: [RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13
,
Alistair Francis
,
20:57
Re: [RESEND PATCH v2 5/5] target/riscv: Reserve exception codes for sw-check and hw-err
,
Alistair Francis
,
20:55
Re: [RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0
,
Alistair Francis
,
20:54
Re: [RESEND PATCH v2 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
,
Alistair Francis
,
20:54
Re: [RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13
,
Alistair Francis
,
20:47
Re: [RESEND PATCH v2 1/5] target/riscv: Reuse the conversion function of priv_spec
,
Alistair Francis
,
20:31
Re: [PATCH v4 1/4] target/riscv: Add functions for common matching conditions of trigger
,
Alistair Francis
,
20:28
Re: [PATCH v4 4/4] target/riscv: Apply modularized matching conditions for icount trigger
,
Alistair Francis
,
20:28
Re: [PATCH v4 3/4] target/riscv: Apply modularized matching conditions for watchpoint
,
Alistair Francis
,
20:27
Re: [PATCH] target/riscv: Use get_address() to get address with Zicbom extensions
,
Alistair Francis
,
20:21
Re: [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations
,
Max Chou
,
11:50
Re: [RFC v2 1/7] hw/core: Make CPU topology enumeration arch-agnostic
,
Markus Armbruster
,
08:25
Re: [RFC v2 1/7] hw/core: Make CPU topology enumeration arch-agnostic
,
Markus Armbruster
,
08:19
Re: [PATCH 4/4] hw/net: Fix the transmission return size
,
Edgar E. Iglesias
,
06:31
Re: [PATCH 3/4] hw/dma: Add a trace log for a description loading failure
,
Edgar E. Iglesias
,
06:22
Re: [PATCH 2/4] hw/dma: Break the loop when loading descriptions fails
,
Edgar E. Iglesias
,
06:21
Re: [PATCH 1/4] hw/dma: Enhance error handling in loading description
,
Edgar E. Iglesias
,
06:19
Re: [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec
,
Fea Wang
,
02:37
[PATCH 3/6] target/riscv: Add MISA implied rules
,
frank . chang
,
02:06
[PATCH 6/6] target/riscv: Remove extension auto-update check statements
,
frank . chang
,
02:06
[PATCH 5/6] target/riscv: Add Zc extension implied rule
,
frank . chang
,
02:06
[PATCH 4/6] target/riscv: Add standard extension implied rules
,
frank . chang
,
02:05
[PATCH 2/6] target/riscv: Introduce extension implied rule helpers
,
frank . chang
,
02:05
[PATCH 1/6] target/riscv: Introduce extension implied rules definition
,
frank . chang
,
02:05
[PATCH 0/6] Introduce extension implied rules
,
frank . chang
,
02:05
RE: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
,
張育銘
,
02:00
[PATCH 4/4] hw/net: Fix the transmission return size
,
Fea.Wang
,
01:48
[PATCH 3/4] hw/dma: Add a trace log for a description loading failure
,
Fea.Wang
,
01:48
[PATCH 2/4] hw/dma: Break the loop when loading descriptions fails
,
Fea.Wang
,
01:48
[PATCH 1/4] hw/dma: Enhance error handling in loading description
,
Fea.Wang
,
01:47
[PATCH 0/4] hw/dma: Add error handling for loading descriptions failing
,
Fea.Wang
,
01:47
Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
,
Alistair Francis
,
01:39
Re: [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations
,
Richard Henderson
,
01:11
June 02, 2024
Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8
,
Daniel Henrique Barboza
,
23:48
Re: [PATCH v6 0/3] Support RISC-V IOPMP
,
Ethan Chen
,
23:47
Re: [PATCH RFC 0/8] Add Counter delegation ISA extension support
,
Atish Kumar Patra
,
02:39
June 01, 2024
Re: [PATCH RFC 0/8] Add Counter delegation ISA extension support
,
Daniel Henrique Barboza
,
05:53
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