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[PATCH RESEND 0/6] Introduce extension implied rules
From: |
frank . chang |
Subject: |
[PATCH RESEND 0/6] Introduce extension implied rules |
Date: |
Wed, 5 Jun 2024 14:31:48 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
implied extensions. This also eliminates the old-fashioned ordering
requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc.,
removing the need to check the implied rules of Zvksg before Zvks.
The idea [1] and the implied rules [2] are referenced from LLVM.
[1]
https://github.com/llvm/llvm-project/blob/main/llvm/lib/TargetParser/RISCVISAInfo.cpp#L875
[2]
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVFeatures.td
Frank Chang (6):
target/riscv: Introduce extension implied rules definition
target/riscv: Introduce extension implied rule helpers
target/riscv: Add MISA implied rules
target/riscv: Add standard extension implied rules
target/riscv: Add Zc extension implied rule
target/riscv: Remove extension auto-update check statements
target/riscv/cpu.c | 396 +++++++++++++++++++++++++++++++++++++
target/riscv/cpu.h | 18 ++
target/riscv/tcg/tcg-cpu.c | 238 +++++++++++-----------
3 files changed, 537 insertions(+), 115 deletions(-)
--
2.43.2
- [PATCH RESEND 0/6] Introduce extension implied rules,
frank . chang <=
- [PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition, frank . chang, 2024/06/05
- [PATCH RESEND 2/6] target/riscv: Introduce extension implied rule helpers, frank . chang, 2024/06/05
- [PATCH RESEND 3/6] target/riscv: Add MISA implied rules, frank . chang, 2024/06/05
- [PATCH RESEND 4/6] target/riscv: Add standard extension implied rules, frank . chang, 2024/06/05
- [PATCH RESEND 5/6] target/riscv: Add Zc extension implied rule, frank . chang, 2024/06/05