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[PATCH v4 1/6] target/riscv: Reuse the conversion function of priv_spec
From: |
Fea.Wang |
Subject: |
[PATCH v4 1/6] target/riscv: Reuse the conversion function of priv_spec |
Date: |
Thu, 6 Jun 2024 21:54:49 +0800 |
From: Jim Shu <jim.shu@sifive.com>
Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c
could also use it.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 1 +
target/riscv/tcg/tcg-cpu.c | 13 ++++---------
3 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 69a08e8c2c..fd0f09c468 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1790,7 +1790,7 @@ static int priv_spec_from_str(const char *priv_spec_str)
return priv_version;
}
-static const char *priv_spec_to_str(int priv_version)
+const char *priv_spec_to_str(int priv_version)
{
switch (priv_version) {
case PRIV_VERSION_1_10_0:
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6fe0d712b4..b4c9e13774 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -830,4 +830,5 @@ const char *satp_mode_str(uint8_t satp_mode, bool
is_32_bit);
/* Implemented in th_csr.c */
void th_register_custom_csrs(RISCVCPU *cpu);
+const char *priv_spec_to_str(int priv_version);
#endif /* RISCV_CPU_H */
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index fa8a17cc60..4c6141f947 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -76,16 +76,11 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu,
uint32_t bit,
static const char *cpu_priv_ver_to_str(int priv_ver)
{
- switch (priv_ver) {
- case PRIV_VERSION_1_10_0:
- return "v1.10.0";
- case PRIV_VERSION_1_11_0:
- return "v1.11.0";
- case PRIV_VERSION_1_12_0:
- return "v1.12.0";
- }
+ const char *priv_spec_str = priv_spec_to_str(priv_ver);
- g_assert_not_reached();
+ g_assert(priv_spec_str);
+
+ return priv_spec_str;
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
--
2.34.1
- [PATCH v4 0/6] target/riscv: Support RISC-V privilege 1.13 spec, Fea.Wang, 2024/06/06
- [PATCH v4 1/6] target/riscv: Reuse the conversion function of priv_spec,
Fea.Wang <=
- [PATCH v4 2/6] target/riscv: Define macros and variables for ss1p13, Fea.Wang, 2024/06/06
- [PATCH v4 3/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0, Fea.Wang, 2024/06/06
- [PATCH v4 4/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32, Fea.Wang, 2024/06/06
- [PATCH v4 5/6] target/riscv: Reserve exception codes for sw-check and hw-err, Fea.Wang, 2024/06/06
- [PATCH v4 6/6] target/riscv: Support the version for ss1p13, Fea.Wang, 2024/06/06
- Re: [PATCH v4 0/6] target/riscv: Support RISC-V privilege 1.13 spec, Alistair Francis, 2024/06/07