[RFC PATCH 0/2] Support RISC-V CSR read/write in Qtest environment

[Ivan Klokov]

These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.

Ivan Klokov (2):
  Add RISC-V CSR qtest support
  QTest example for RISC-V CSR register

 target/riscv/cpu.c             | 13 +++++++
 target/riscv/cpu.h             |  3 ++
 target/riscv/csr.c             | 49 +++++++++++++++++++++++-
 tests/qtest/libqos/meson.build |  3 ++
 tests/qtest/libqtest.c         | 27 ++++++++++++++
 tests/qtest/libqtest.h         | 14 +++++++
 tests/qtest/meson.build        |  2 +
 tests/qtest/riscv-csr-test.c   | 68 ++++++++++++++++++++++++++++++++++
 8 files changed, 178 insertions(+), 1 deletion(-)
 create mode 100644 tests/qtest/riscv-csr-test.c

-- 
2.34.1