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[PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filter
From: |
Atish Patra |
Subject: |
[PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties |
Date: |
Wed, 26 Jun 2024 16:57:23 -0700 |
From: Kaiwen Xue <kaiwenx@rivosinc.com>
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4760cb2cc17f..ef50130a91e7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -178,6 +178,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
+ ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
@@ -1467,6 +1468,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
+ MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false),
MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index fb7eebde523b..b1376beb1dab 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -74,6 +74,7 @@ struct RISCVCPUConfig {
bool ext_ztso;
bool ext_smstateen;
bool ext_sstc;
+ bool ext_smcntrpmf;
bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
--
2.34.1
- [PATCH v7 00/11] Add RISC-V ISA extension smcntrpmf support, Atish Patra, 2024/06/26
- [PATCH v7 01/11] target/riscv: Combine set_mode and set_virt functions., Atish Patra, 2024/06/26
- [PATCH v7 02/11] target/riscv: Fix the predicate functions for mhpmeventhX CSRs, Atish Patra, 2024/06/26
- [PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties,
Atish Patra <=
- [PATCH v7 04/11] target/riscv: Add cycle & instret privilege mode filtering definitions, Atish Patra, 2024/06/26
- [PATCH v7 05/11] target/riscv: Add cycle & instret privilege mode filtering support, Atish Patra, 2024/06/26
- [PATCH v7 06/11] target/riscv: Implement privilege mode filtering for cycle/instret, Atish Patra, 2024/06/26
- [PATCH v7 07/11] target/riscv: Save counter values during countinhibit update, Atish Patra, 2024/06/26
- [PATCH v7 08/11] target/riscv: Enforce WARL behavior for scounteren/hcounteren, Atish Patra, 2024/06/26
- [PATCH v7 10/11] target/riscv: More accurately model priv mode filtering., Atish Patra, 2024/06/26
- [PATCH v7 09/11] target/riscv: Start counters from both mhpmcounter and mcountinhibit, Atish Patra, 2024/06/26
- [PATCH v7 11/11] target/riscv: Do not setup pmu timer if OF is disabled, Atish Patra, 2024/06/26